JPS58114136A - Memory controlling system - Google Patents

Abstract

PURPOSE:To facilitate changing specifications of instructions and processings, by providing a device, where execution stop indicating flags corresponding to addresses of a control storage device are stored, in a slave processor of a computer system and changing these indicating flags by a master processor. CONSTITUTION:A computer system is provided with a master processor 11 and a slave processor 12, and the processor 12 is provided with an indicating flag storage device 13, a controlling circuit 14, a control storage device 15, a microinstruction register 16, etc. Execution stop indicating flags corresponding to addresses of the storage device 15 are stored in the device 13; and when the system is operated by the storage devie 15, the execution is stopped quickly if the flag of the device 13 is set. This execution stop is detected by the processor 11, and the processor 11 changes contents of the register 16 by the execution stop, and the processor 12 is started by the processor 11. Thus, the change of specifications of instructions and processings is executed easily by the processor 11.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention uses a read-only memory (R) as a control storage device.
(2) Conventional technology and problems Conventionally, there is no means to adjust and control the instructions in the CFi and ROM in nine processors using the control memory KROM that stores microinstructions. Therefore, changes in microinstruction specifications,
There was a drawback that the ROM had to be converted in order to change the processing.

(3) Purpose of the Invention The purpose of the IIA is to eliminate the above-mentioned drawbacks and provide a method for flexibly dealing with changes in specifications and processing of the microinstructions. (4) Structure of the Invention This purpose is to , in a computer system consisting of a master processor and a slave processor, the slave processor is provided with an instruction flag storage cap that stores an execution stop instruction flag corresponding to the address of the control storage device of the slave processor, and the instruction flag storage! il is arbitrarily set by the master processor, and when the slave processor is operating according to the control storage device, if the corresponding execution abort flag is on, it immediately aborts execution, while the master processor , means for detecting that the slave processor has stopped by determining an execution stop instruction flag; and when the slave processor is stopped, the master processor changes a microinstruction register of the slave processor to cause the slave processor to stop. and means for stopping the slave processor when the slave processor attempts to execute an instruction with the flag based on the execution stop flag of the slave processor, and stopping the slave processor while the slave processor is stopped. The embodiments of the present invention are as follows: An actual example will be explained in detail using the drawings. The diagram shows a functional block V showing an embodiment of the present invention. In the diagram, li#:t master processor (MCPU)
.

12 is a slave processor (SCPU); 13 is an instruction flag storage device; 14 is a control circuit; 15 is a control storage device f
l (ROM), 16 is micro instruction register (MIR)
, 17u multiplexer A318 is w, n=teplexer B0 where 15 is also simply referred to as memory.

In a system where the master processor 11 has 32 bits of data and the slave processor has 12,664 bits of microinstructions, the slave processor 12
The instruction flag storage device 13 and the control device 14 that instruct to stop execution, the function of determining the flag and halting (stopping) the 5 CPU 12, the 64-bit O instruction register 16, and the instruction when the 5 CPU I2 stops. An instruction is taken out from the MCPU II and set in the register 16 by the i Lunaplexer 16.17. The MCP
The data set from U11 to the instruction register 16 is divided into 2 times of 32 bits each (for example, Lunaplexer 16ti
The lower bit, the multiplexer 17 sets the upper 32 bits) to 0. Also, the MCPU II has a function to detect that the 8 CPU 12 has halted due to the execution abort flag, and the 5 CPU 12
In a computer with processors in the mask-slave relationship, the slave side normally handles high-speed calculations, and the mask side performs system control.In the present invention, the microinstructions of the 5CPUs 12 It is assumed that the next address (Next address) is specified by the ONA section of the microinstruction register 16.

To further explain the operation example in detail, when there is a change in the contents of the address (address a) of the control memory bag flli15 in the 5CPU 12, the execution stop instruction flag memory device fl1
Set the flag of address a in 3 to ON ('1'), 5
The CPU 12 microinstruction reads tNA (Next Add) the next microinstruction from the control storage 115.
It has a field called resa).

Therefore, when # reads the address a, NAP! It! 0, that is, N
If b is a microinstruction whose A part has a value of a, the instruction execution order is b→a.

Address a of the control storage device 1115 and the execution stop instruction flag storage device 13 is addressed as 0, but since the execution stop flag read from the execution stop instruction flag storage device [1B is 1'', the execution stop instruction flag storage device 13 is 13yo, 6b
After executing the instruction, the CPU 12 stops.

5CPU12 stops (halt) with execution stop flag
When the master processor 11 detects that the micro-instruction register 1 has changed the micro-instruction, the master processor 11 sends the micro-instruction instruction to the address a of the control memory of the FiSCPU 12.
6 and starts the 5CPU 12 @As a result, the 5CPU 12 starts the master processor 1 instead of executing the instruction at address a of the control storage device 115.
The instruction set from 1 to 0 is executed and the desired processing is performed.In addition, the microinstruction register 16 has 64 bits, and the data bus of the master processor 11 has 32 bits.
Since it is a bit, the master processor 11 to 5 CPU12
The microinstruction register 16 is set twice.08 The address at which the CPU 12 stopped the execution flag is determined by always saving NAL5, which was executed one step before. For example, if a register is provided so that the master processor 11 can refer to it, the master processor can know it. (6) As described in detail, according to the present invention, the control storage device This method is particularly effective for computers using read-only memory (ROM), and is effective in that it can flexibly respond to changes in microinstructions, etc., without replacing the ROM.

[Brief explanation of the drawing]

The figure is a functional block diagram showing one embodiment of the present invention.O Explanation of symbols: 11 is a master processor (MCPU);
2 is a slave processor (SCPU), 13 is an instruction flag storage device t, 14 is a Fi control circuit, and 15t'! control memory (ROM), 16 is a microinstruction register (MIR);
), 17 is! Multiplexer A, 18 to multiplexer B
. i'5

Claims (1)

[Claims] In a computer system consisting of a master processor and a slave processor, the slave processor is provided with an instruction flag storage lid for storing an execution stop instruction flag that covers the address memory of a tllllJlill storage lid of the slave processor; The device is optionally configured by the master processor, and the slave processor, if operating according to the control storage attachment, immediately stops execution if the corresponding execution stop flag is on, while the master processor: means for detecting that the slave processor has stopped by determining a stop command flag; and when the slave processor is stopped, the master processor changes the microinstruction register of the slave processor, and the slave processor and means to stop the core slave processor when the slave processor is about to execute an instruction with the flag according to the execution stop flag of the slave processor, and while the slave processor is stopped. A memory control method characterized by comprising means for starting the slave processor after changing the contents of the instruction register of the slave processor.