JPS58110075A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a high gain-band width as well as to obtain a high frequency transistor which generate no short-circuit between electrode wirings even when its base-collector P-N junction capacity is small by a method wherein the emitter-base junction surface is made flat, and the base-collector area is also made small. CONSTITUTION:An N<+> type buried layer 32 is provided on a P type Si substrate 21, an N type layer 33 is epitaxially grown on the whole surface, and the layer 33 is isolated into an island-like form using an SiO2 film 25a. Then, an N type collector wall 34 is formed on the circumference of the layer 33, this part is covered by an SiO2 film 35, a polycrystalline film 27 is deposited on the whole surface, and a BSG film 28 is provided at the part facing the wall 34. Subsequently, the boron in the film 28 is diffused by performing a heat treatment, a P<+> type region 38 is formed, a diffusion is performed on the wall 34 by pressing-in, and the layer 33 is connected to the N<+> type layer 32. Then, the layer adjoining the region 38 is removed, a P type region 40 is formed by diffusion in the exposed layer 33, and an N type emitter region 24, which is pinched by a P type base region 42, is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same.

Conventionally, as a manufacturing method for obtaining a transistor with a flat emitter-paste junction, a process shown in the first example or C) has been proposed.

The steps of this manufacturing process are as follows.

(1) An n+ type buried region 2 is formed on a p-type 5i substrate 1, and an n-type epitaxial layer 3 is formed. and p-type isolation region 4en+ type collector all region 5. Thickness 30.9
A S t 0,2 film 6 of tm is formed. Then, the pace forming region 05in2II6 is removed, a diffusion window 7 is formed, and a polycrystalline Si film 8 with a thickness of about 0.2mm is formed.
Form an n+ type region 9 with a diffusion depth of approximately 0.2 cm using the polycrystal 5 as a diffusion source in the region 7.
Figure 11).

(2) Next, the thickness is about 0. A 13N4 film 10 of Q6#L is formed, and S is formed on the emitter formation region by photoetching.
The polycrystalline 5 is removed by etching away the film 8 and the n+ type region 9, leaving the i 3N and 10 layers and using the S i , N and film 10 as a mask. Then, the epitaxial layer 3 exposed in the diffusion window 7 is oxidized to a thickness of about 0.15m05iO2 film 11.
form. And about 160 Key, about 1 cutting Q-i
Boron ions are implanted at on s/7. In this way, a p-type space region 12 with a thickness of about 0.1 μm is formed directly under the n+ shadow region (emitter region) 9′, and a p-type space region 12 with a thickness of about 0.3 μm is formed in the Si02 film 11+ region F. A region 13 is formed. Furthermore, about 60 KeV, about I x 10 s
Now 15 g of boron is ion-implanted, and the SiO2 film 11 is
1: Form a p shadow area 14 below (1μ1 figure (average).

(3) Next, when annealing at 1000°C, the sheet resistance is approximately 180 Q/gate p+ type base contact region 15
is formed. Then, Si, N, III 10 is removed, a base contact window and a collector contact chamber are formed, and a base At layer 1116. Emitter M wiring 17. A collector M arrangement 18 is formed (FIG. 1(C)).

However, in the transistor obtained by K in this way, the paste formation area overlap + shadow area 9 is removed,
KM arrangement 11 because the SiO2 film 6 is about 0.9#sL
6,170 steps '1ist9.20? ", the U wiring has a high disconnection rate. Also, in order to prevent the sheets of M wiring 16 and 17, the distance X between the %M wiring must be set to 2 to 3. must be 2-3 times larger than the base contact window, which is 2-3 times wide, so the width of the pace M thread 16 will be 4-6 shoulders. It should be about one cotton swath outside of the 9' end. Therefore, A
When adding 2 to 3 meters of the t-width #1t11 distance X, the base contact region 150 width y becomes 7-1G#w&. Therefore, the area of the base contact region 150 becomes large,
The pace-collector junction capacitance increases and the high frequency characteristics deteriorate. Furthermore, if the thickness of the SiO2 film 6 is reduced in order to reduce the step difference, the epitaxial layer 3 directly under the *StO film 6 into which boron ions are implanted at 160 KeV is inverted to p-type.

In addition, since the ttc and ht wiring is formed on an uneven surface, when dry etching is performed using CCt, gas, etc., M remains at the stepped portions, increasing the Ou wiring shedding rate and reducing the yield. decreases.

However, the purpose of this invention is to obtain a high fT with a flat emitter-pace junction, and to achieve a high fT.

PN between the pace and the collector by reducing the area of the collector.
It is an object of the present invention to provide a semiconductor device including a high frequency transistor in which no seam occurs between electrode light distributions despite the small junction capacitance K, and a method for manufacturing the same.

An embodiment of this invention is shown in FIG. 2 (A) 1 to (Fl and (
4) - (shown as a leopard. In other words, this semiconductor device is a semiconductor integrated circuit device including a transistor with a flat emitter-paste junction, and as shown in FIG. 2(I')K,
A collector 22 is formed by sequentially laminating layers on a p-type S1 substrate 21.
A base contact region 26 formed from the base 23 and the emitter 24 to a boundary between the base 23 and an isolation oxide film 25a formed on a separate substrate 21, and a 1arR film 25m formed in the portion of the base contact region 26.
A space leader line consisting of a polycrystalline 5i film 27a formed horizontally from a partial region close to the boundary with the surface of the isolation oxide film 251; - the oxide films 28 and 28b covering the space drawer II (polycrystalline 5i film 27a) and the isolation oxide film 251 of the oxide film 28m;
A nine-pace Affi sheet 29 formed in a corresponding portion and bonded to the pace leader line (polycrystalline 5i film 271) via a running gap, and an emitter At bonded to the upper surface side of the emitter 24.
a pipe 30 and a collector A joined to the collector 22;
Jf! 41I31, and the oxide films 28 and 28b
Among them, FM27 according to the multi-connected product forming the pace leader line.
The III region covering the polycrystalline film 27m is made up of a 5in2II (BSG film) 281 containing boron, which is used as a diffusion source for the polycrystalline film 27m, and the other region Ii is made of a FiS102 film 28.

This semiconductor device is manufactured by the following procedure.

Note that (5) to (F) in FIG. 2 are plan views of the semiconductor substrate in each step, and (A to (F) are cross-sectional views corresponding to the plan views.

(1) First, attach the p-type 10 to 20ρ S-arc substrate 21 to the ♂
A shape-embedding chain *32 is formed. Then, an n-type epitaxial layer 33 of about 0.691 nm is formed with a thickness of about 1.5 μm. Then, another isolation oxide film 25m is formed using an insulation isolation technique. Approximately 0.5 in thickness by heating oxidation method or shake CVD method
A 5IO2 film 25b of μ chicken is formed (section 2 in Figure 2).

(A’)).

(2) Next, using selective diffusion technology, the male-shaped collection 11 [
*(El-form collector quaol) 34 is formed.

Then, the base forming vertical plate 5i02[35 is removed to form the base diffusion window 36 (Figure W52 (B), (target)).

(3) Next, a polycrystalline Si film 27 with a thickness of about 0.2 diodes is formed. Furthermore, a boron-containing Si〇- (hereinafter referred to as a BSG film) 2811 with a thickness of about 0.4 μm is formed on top of this. Then, a part of the base diffusion window 36 (width C is about 2 degrees) and the isolation oxide film 25a are formed by photo-etching.
The BSG film 28a is left on top (FIG. 2(C), (σ)).

(4) Next, about 7X15 1 ounces at about 100 KeV
/aj.

Inject AJ ions. Then, A$ is injected into the crystal 5i film 27 except immediately below the BSG film 2 film layer 8. and,
Form an OCVD 5in2 film 37 with a thickness of about 0.1m,
Heat at 1000° C. in N2 gas atmosphere. Then B
The polycrystalline 3i films 27 of the SG film 281 become p+ type polycrystalline 3i films 271, and the remaining polycrystalline Si films 27 become n+ type polycrystalline 5 films 27b. And base diffusion W1
Directly below the r shadow crystal 5i film 271 in the 36 region! /c is a sheet resistance of approximately 150ψ.

A p+ type region 38 with a diffusion depth of about 0.5 psi is formed, and an n+ type crystalline film 27b [below has a sheet resistance of about 40 ψ].
mouth, diffusion depth approximately 0. An n+ type region 39 of IIRIL is formed. As a result, a region is formed in the polycrystalline 5i just below the edge 8 of the BSG film 281 where both boron and sAs are diffused. Further, the n+ type collector region (collector all) 34 is in contact with the n type buried region 32 (Fig. 2 (2), a
ly)).

(51 then about 120 KeV e I X 10 1
Ons/cs+ boron ions are implanted from the substrate surface. Then, the male shadow area 39 [bottom base width approximately 0.08
A p-type space region 40 of tm is formed. On the other hand, the surface of the n-type epitaxial layer 33 is a C shadow crystal 5i film 27b,
It is not prevented by the 5i02 film 35 from being inverted to p-type. In other words, the Ksto□ film 35 is
The thickness must be determined (Fig. 2 (8)).

(6) Next, the SN3'4 film 41 with a thickness of about 0.06mm
form. Then, by photoetching, Si, N, film 41a and isolation oxide film 25 in the emitter formation region are removed.
The Si3N4 film 41b is also left on a-1. BSG film 281
The distance sd between S'T3N4 and S'T3N4 is approximately II! Let it be rIL (Figure 2), (B)).

(7) Next, using the BSG film 2 layer 8 layer a13N4 film 41 as a mask, the n+ type crystal Si pattern 27b and the n+ type region 39 are etched with a HNO3 and HF mixed solution, = 5t.
3N, the n shadow crystal Si@27b, its 'FKn+ type emitter, and the ivy region 24 are left under the film 41alt. Also Si3
N, N+ type polycrystalline Si directly under the film 41a! II 27b
, the p+ type polycrystalline film S1 film 271 remains under the BSG film 28a LT. In this case, the wet etching method is used to greatly reduce the side etching and take advantage of the fast etching speed of the n+ type polycrystalline 5i film 27b a n+ type region 39 (even if slightly overetched, the n type Etching does not progress to 33), increasing the etching accuracy in the depth direction. Even if the t+, p shadow region 40 is etched, it will form a p shadow region in a later step, so there is no need to overetch it (FIG. 2 (G')).
.

(8) Next, heat treatment is performed in an oxidizing atmosphere at 900-1000°C to convert the n-type epitaxial layer 36 surface [frK thickness 0, 15 direction fJs 102 film 28b] into n+ type p+
Side surface of polycrystalline 5i film 271° 27b and emitter 2
A 5in2 film 28b having a thickness of about 0.2p and a thickness of 11iK on the 40th side is formed. Then about 60KeVslX10
Foil/cdo bo':/l ions are implanted to form a p+ type region 42 directly under the SiO2 film 28b (see Figure 2).
.

(9) Next, annealing treatment is performed in N2 gas, and the p
A me-shaped base contact inclined wall 26 having a depth of 150 ρ and a depth of 0° 3 μ is formed in the +-shaped region 2. Next, 5i3N411
141i′f: Remove to form emitter contact window and isolate oxidized $25 m by photoetch technique.
A part of the old G film i is removed to form a base contact 113 so that the shadow crystal Sil[27a and the M wiring are in contact with each other. Similarly, the S i 02 membrane 3 on the collector area 34
5 is removed to form a collector contact $44, and the paste M wiring 29. Emitter M wiring 30 and collector M
Wiring 31 is formed. And the type 1 region directly below the emitter 24 is at an active base of 23 degrees? The shape chain region becomes the emitter 24. Front, emitter-base junction side 5to2*zs
b (Fig. 2 (y) * (l')).

Therefore, the width f of the base contact region 26 shown in FIG. 2(1') is equal to the width C shown in FIG. 2(G') and the width d shown in FIG. 2(F'). The sum of the dimension & of e shown in FIG. 2 (σ) results in a width of 4.5 −, making it possible to reduce the total area of the base region.

However, since the base contact slope 26 is formed on the polycrystalline Si film 27Jl of the split layer oxide film 251, the distance between the Al wirings 29 and 30 can be set to about 2.5 #L. Furthermore, the polycrystalline film 2 below the edge g of the BSG film 28m
7a t n + shape region 39 Since etching has occurred, M force is applied to this step! Even if it sticks, it will be separated in the middle. Therefore, when forming the M wiring 29°30, even if the resist no. It can prevent
t-wiring-1) ratio can be significantly reduced.

Since the wires are placed on the Sarani, base, and emitter AjEi129.3Qti moxibustion crystal Si films 27!1.27b, the unevenness is small and there are no sudden steps, which can greatly reduce the probability of disconnection of the M wiring. A using CCV, etc.
During the dry etching of t, fine Al1<turns can be formed with a high yield because no gaps are generated between At at the step portion.

Furthermore, when manufacturing a semiconductor device using this manufacturing method, it is possible to manufacture a semiconductor device having the above-mentioned characteristics with high accuracy and high yield.

In the above manufacturing method, the polycrystalline 5 is coated with the film 27b using a mixed solution of HNO3 and HF in the step shown in FIG. 2 (G').
Instead of etching the n'' shadow area 41, CF, I
Deodorized etching or lid etching using C3F8 gas or the like may also be used.

9, p”N polycrystalline S1 film 271 e p”* region 38
*n” shadow crystal 5i film zyb e p”ffe region 26
゜p shadow area 40゜n+ shaped area 39 can be used as a resistor, so it is sufficient to use one with a desired sheet resistance as a resistor. Furthermore, it is difficult to use an amorphous 5i film instead of the polycrystalline Si film 270.

As described above, the semiconductor device of the present invention includes a collector, a base, and an emitter that are sequentially stacked on a semiconductor substrate. A memento base contact region formed on the 111I semiconductor substrate from the boundary of the isolation insulating film to the base, 1ilFIa to x:l
:/! IB drawn horizontally from a partial axial region near the boundary with the isolation insulating film in the 51st region to the surface of the isolation insulating film.
The formed polycrystal 5 is connected to a base lead line made of a film, and IIu
an insulating film that leaves the upper surface of the emitter and covers its side surface, a base contact region, and a pace lead wire, and a pace electrode that is connected to the pace lead wire through an opening formed in a portion of the insulating film corresponding to the separation insulating film. Since the emitter electrode is connected to the upper surface of the iiT emitter and the collector electrode is connected to the collector, the emitter-pace junction is flat and a high fT can be obtained. It is possible to obtain a semiconductor device including a high-frequency transistor with a small area and no sheet between electrode wirings despite the small pn junction capacitance between the pace and collector, and also to manufacture the semiconductor device of the present invention. The method includes applying a base layer to a predetermined region of the covering insulating film portion of a first insulating film, which includes an isolation insulating film portion surrounding a predetermined island region on a first conductivity type semiconductor substrate and a covering insulating film portion covering the upper surface of the island region. a diffusion window forming step of opening a diffusion window; a polycrystalline Si film forming step of forming a polycrystalline Si film on the semiconductor substrate so as to partially cover the upper surface of the isolation insulating film portion of the first insulating film;
A second insulating film forming a ts2 insulating film containing impurities for forming a second conductivity type on a III polycrystalline 5i film extending from a region near the boundary of the isolation insulating film part of the diffusion window to above the isolation insulating film part; forming a first conductivity type region in a region corresponding to the diffusion window except under the second insulating film;
A first diffusion step of forming second conductivity type regions under the conductive film, and diffusing second conductivity type forming impurities into the pace diffusion window to form a second conductivity type base region directly below the first conductivity type region. a second diffusion step of forming an oxidation-resistant film in the emitter formation region of the polyhedral Si film exposed in the base diffusion window; The Iff polycrystalline 5i film and the first conductivity type region are etched away using as a mask, and the remaining first conductivity type region is used as an emitter, and the etching process surface is oxidized! a base contact region forming step of forming a s3 insulating film and implanting ions through the third insulating film to form a base contact region of a second conductivity type under the ts2 insulating film and the third insulating film; 2 Insulating film!
(iii) A pace electrode forming step in which an opening is formed in the area corresponding to the separated insulating olfactory part and a pace electrode is bonded to the polycrystalline Sil through this opening, and the oxidation-resistant film is removed and an emitter is formed through the R bulletin crystal 5i film. By combining the emitter electrode forming process in which the emitter electrode is bonded to the collector and the collector electrode to the collector, the semiconductor device described above can be manufactured with a high yield of 9 and high precision! l
It has the advantage of being able to be manufactured in large quantities.

[Brief explanation of the drawing]

1) is an explanatory diagram of the manufacturing process of the conventional example, and Figures 2 and 2 are a plan view and a cross section of an embodiment of the present invention. It is a manufacturing process explanatory diagram shown in a figure. 21... p-type 5i substrate (semiconductor substrate), 22... collector, 23... pace, 24... emitter,
251-9#II oxide film (isolation insulating film part), '25i
)--5i02 film (covering insulating film part), 26... base contact region, 271... n+ type polycrystalline 5i film,
27b...p+ type polycrystalline 5i film, 28a...BSG
Film (second insulating film), 28b-...s to2 film (third insulating film), 29・<-Xkt arrangement, IN (pace electrode), 3
゜...Emitter Aj arrangement W & (emitter electrode), 31.
... Collector Al wiring (collector electrode), 32 ... Meter-shaped buried layer, 33 ... N-type epitaxial layer, 35.
...5io2qa. 36-...diffusion window, 37-CVD 5to2 film, 38-
p+ type region 59-n1 type region, 40 ・p type pace region, 41S13N4 film, '2...p+ type region 4
3...Base contact window, 44...Collector contact window procedural amendment (method) May 10, 1980 Patent Application No. 212391 Bow 2, Title of invention Semiconductor device and method for manufacturing the same 3 , Relationship to the case of the person making the amendment Applicant's address: Kadoma 1, Kadoma City, Osaka Prefecture, Osaka Prefecture
2) Matsushita Electric Industrial Co., Ltd. Representative 111 Toshihiko Shimo 4, Agent 5 Date of hli positive order 1981 4
Month 9th (1) Statement 1N? 1st line or 2nd line of the page, "No. 211 (A) - CF) #! Hi (16 - (II
J, %6or IFI 2W (Al-(F) # and (a) to (1)" is corrected. (2) On page 117 of the specification, line 4, it says "Figure 2 (leopard)" amended as "rflK2 Figure 0)" 2. (3) In the specification lN8111I line I, "(IcJ~(1)" is corrected as "(a)~(1) is"). (4) Specification Page 8, 11N, lines 15 to 16,
``Figure 2 (A), (4J) ``Figure 2 prisoner, (i)
Correct it with J. (5) Specification, page 8, line 20, rlN2 diagram (81, (
IJ is corrected to ``Figure 2 (B), (b) J. (6) Specification page 117, line 6, rl!Figure 2 (C)
, ((j
Correct it with J. (7) Specification, page 10, line 2 to line 1113, “
Figure 2 (D), (B)" was replaced with "Figure 2 (II,
(d) Correct J. (8) Specification No. 10j [Line 11, "Fig. 2 (chain") is corrected to "Fig. 2 (C)". (9) Specification page 1110, Line 16, rl Fig. 12 ( 2)
). (Me) is corrected as "Figure 2 (E), (f) J. (10) Specification @ page 11, line 1'1, "Figure 2 (α)''
A certain rl12v! Correct it as J(g)J. 01) 1oll@page 11, line 19, correct it as "rfMg diagram (h) for the 2nd m section." (12) Page 12, line 13 to 14f of the specification? ″
Eye, ``2nd figure (F), (wa'') is ``2nd rlJ
(El), (1)”. (13) Book IIJI 11112 j [II l 5
Line l, rl12m(1')J is ``II2(I)
” he corrected. (14) Specification page 12, line 16, r Figure 2 (C!I
Correct the text "J" to "Figure 2 (C)". (15) Page 12, line 17 of the specification, “Figure 2 (B)”
The text has been corrected to read "Figure 2 (f)". (16) Specification lll12j[lN line 17, “Second
11 (Correct cAJ to "Figure 2 (g)". (17) #i Specification II! Page 14, line 112, rlN2
(18) In the 10th line of page 17 of the specification, the phrase ``Figure 2 (6) or 0 is'' is changed to ``Figure 2 (a) or 1)
I am corrected. (19) The figure numbers "(4) to (wa)" in Figure 2 of the drawings are corrected to "(a) to (1)" in the attached red book.

Claims (2)

[Claims] (1) Nine collectors are formed by sequentially laminating them on a semiconductor substrate. Base and emitter and 1! A space contact region F'a formed from the boundary of the isolation insulating film formed on the Ir-generated semiconductor substrate to the base, and a part of the base contact region near the boundary with the isolation insulating film to the isolation insulating film a base lead line made of a polycrystalline SM film drawn horizontally over the surface; an insulating film covering the side surfaces of the emitter, leaving the upper surface thereof, a base contact region, and the base lead line; and an insulating film corresponding to the isolation insulating film. A semiconductor device comprising: a base electrode formed in a portion thereof and connected to the base lead line through an opening; an emitter electrode connected to the upper surface side of an ltI emitter; and a collector electrode connected to an fMJ collector. . (2) A base on a predetermined region of the LTL distribution ridge insulating film portion of the 1s1 insulating film, which is composed of an isolation insulating film portion surrounding a predetermined island region on the first conductivity type semiconductor substrate and a covering insulating film portion covering the upper surface of the island region. A diffusion window forming step of opening a diffusion window, and the above! s
Kl so that a part of it covers the upper surface of the isolation insulating film part of the
Polycrystalline S to form a polycrystalline 5i film on a tre semiconductor substrate
! In the film forming step, an impurity for forming a second conductivity type is included on the II polycrystalline SM film extending from above the region near the boundary of the isolation insulating film part of the diffusion window to above the isolation insulating film part! a second insulating film forming step of forming an s2 insulating film, and forming a first conductivity type region in a portion of the 1tIe diffusion window corresponding region except under the second insulating film and a second conductivity type region under the second insulating film, respectively. a first diffusion step to form a second conductivity type forming impurity into the pace diffusion chamber to form a second conductivity type immediately below the it+ period @1 conductivity type region;
A second diffusion step to form a conductive type base region and expose the base diffusion 1KK! ? An oxidation-resistant film is formed in the emitter formation region of the U-coupled polycrystal 5i11, and the polycrystal 5 and the first conductivity type region are removed by etching using this oxidation-resistant film and the second insulating film as masks. an etching process to make the 's1 conductive area region mitter, and the etched surface is oxidized to form an @3 insulating film, and ions are implanted through this third insulating film to form the second insulating film and lIT.
A base contact region forming step of forming a second conductivity type pace contact region at the bottom of the third insulation layer;
2. A pace electrode forming step in which an opening is formed in the divided insulation region of the insulation region, and a pace electrode is bonded to this opening. A method for manufacturing a semiconductor device, including an emitter electrode forming step of bonding an emitter electrode to an emitter via a polycrystalline Si film, and a collector electrode forming step of bonding a collector electrode to a collector.