JPS58108737A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to form a highly reliable P-N junction which terminates on the side same as a relatively thick oxide by a method wherein, when the P-N junction is formed in an island-shaped semiconductor region, the formation is performed without removing an oxide film. CONSTITUTION:A P type silicon epitaxial layer 8, which is almost flat, is formed on an N type silicon substrate 800, and then a thin oxide film 802 and a silicon nitride film 803 are formed (diagram A). Then, a selective etching is successively performed on the silicon nitride film 803 and the oxide film 802, and another etching (diagram B) is performed on the exposed part of the P type epitaxial layer 807 using the remaining silicon nitride film 803 and the oxide film 802 as a mask. Then, thermal oxidization is performed using the remaining silicon nitride film 803 as a mask, and a thick oxide film 801 is selectively formed. At the point when the above process has been finished, a selective oxide film 801 which is penetrating from the P type silicon epitaxial layer 807 is formed, and has a result, the P-N junction between the epitaxial layer 807 and the substrate 800 is terminated with the thick oxide film 801 (diagram C). Then, the silicon nitride film 803 is removed, and successively, the P type silicon epitaxial layer 807 is covered by a thick silicon oxide film 820 which was obtained by growing the silicon oxide film 802 appearing on the surface (diagram D).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having a structure in which an element or a part of an element is separated by an oxide, and particularly a method of terminating at least two PNm junctions in such an oxide. Regarding.

For miniaturization of semiconductor devices, thick oxides are used between devices or! Semiconductor devices with a separated structure have recently begun to be used. In such semiconductor devices, it is relatively easy to provide only one PN junction terminated with a thick oxide, so it is put into practical use, or two or more PN junctions are relatively easy to provide, or two or more PN junctions are relatively easily provided. It was very difficult to close them and terminate them on the same side of the thick oxide.

With conventional technology, the spacing between adjacent PN junctions, especially in the 11 minutes terminating in the oxide, cannot be sufficiently controlled. This is to do so.

Therefore, it is an object of the present invention to form two or more PN junctions with high reliability, terminating on the same side of a relatively thick oxide selectively provided on the main surface of a semiconductor. The purpose is to provide a method.

The present invention is based on the knowledge that the reason for the inability to control the PN junction spacing in the prior art is the removal of the insulating layer on the surface of the region where the PN junction is to be formed. In semiconductor devices in which thick oxide is selectively provided, when removing the insulating film on the surface of the semiconductor region, a hammer is used to remove the surface of the thick oxide. The removal exposes not only the surface but also the shoulder portion of the semiconductor region, and since impurities are introduced therefrom as well, the formed PN junction bends sharply and deeply at the end of the oxide. When the surface of the semiconductor region is exposed again in order to create two or more PNM couplings, the shoulder portion is more exposed, and the second PNM coupling is caused by the oxide-terminated portion being even more severely refracted, leading to This is accomplished by making the distance between the PN junction and the PN junction extremely small or zero.

In view of this, the present invention provides a method for manufacturing a semiconductor device that makes it possible to form a PN junction without ever exposing the surface of the semiconductor region to be formed so as to eliminate the PN junction and terminate it with an oxide. This is what we are trying to provide. This reduces the tendency of the PN junction to bend at the termination to the thick oxide, and allows the PN junction to be spaced ft.
+lI can be controlled, and the spacing between the ends of the two PN junctions is kept the same as the spacing elsewhere, providing complete reliability.

A feature of the present invention is that at least two PN junctions are terminated in a semiconductor region surrounded by a relatively thick oxide selectively buried in one main surface of a semiconductor substrate or on the same @plane of the thick oxide. S? J! In the method for manufacturing a semiconductor device having i, one of the PN junctions is formed between a semiconductor substrate and an epitaxyal growth film formed on the semiconductor substrate, and the other one exposes a surface of a semiconductor region. The method of manufacturing a semiconductor device involves the introduction of impurities from the outside.

Further, in the method for manufacturing a semiconductor device, one PN junction formed by introducing impurities from the outside among two PN junctions that terminate on the same side surface of the thick oxide of the semiconductor region surrounded by the thick oxide. However, the thin region of the insulating layer covering the surface of the semiconductor region is completely converted into a cuff layer by heat treatment in a gas containing impurities, and the impurity is diffused into the semiconductor region from the cuff layer. can.

In order to make the principle, purpose, and characteristics of the present invention clearer, the present invention will be explained in detail with reference to the drawings. As shown in FIG. 1A, the surface of the semi-dedicated substrate or epitaxial layer 1 is first oxidized to a
A thin oxide 2 of about 000A is formed, and an SL and IN4 film 3 is provided with a thickness of about 1000 to 2000A. This 8isNa film 3 is further selectively removed using hot phosphoric acid using the silicon oxide film 4 provided thereon as a mask. Next, using this 5isNa film 3 as a mask, a relatively thin isolation oxide 5 of about 1 to 2 microns is formed by oxidation at a relatively low temperature for a long time, leaving an island-shaped semiconductor region 1'. In this case, in order to flatten the surface after oxidation, the portion of the semiconductor material 1 to be oxidized is removed to a predetermined depth in advance. Next, as shown in FIG. 1B, a silicon oxide film 4 (!: S is Na BQ3
A silicon oxide film 6 having a thickness of about 3000 to 4000X is formed on the surface of the active region 1'. A photoresist for forming the first PN junction is then provided, and the oxide film 6 is selectively removed. At this time, the edge of the photoresist 7 is positioned so as to extend to the part of the separated atomized compound region 5 in order to have a large alignment margin and to take advantage of the orientation point of the self 7 line.

For this reason, when the oxide film 6 on the surface of the active region 1' is removed, part of the thick oxide 5 is also removed at the same time as shown at 8 in FIG. 1C. Part S of "waste" is exposed. In this state, the first diagram shows
Diffusion of impurities from the exposed surface of the active head 1'
form a long union 9. As a result, the portion 9' of the first PN junction 9 formed in the active region, which terminates in the thick oxide 5, is bent downward due to excessive diffusion. Such deformation occurs because the self-alignment between the island-like active region 1' and the buried oxide film 5 is utilized when the silicon oxide layer 6 is selectively removed in FIG. 1C. . That is, when the silicon oxide film 6 on the surface of the island region 1' is removed using the photoresist 7 as a mask, the buried oxide film 5 is excessively removed along the shoulder S of the island region 1'. It is. This phenomenon always occurs in order to completely remove the silicon oxide layer 6 on the surface of the island-like region 1'. Next, an oxide film 10 of about 3000 to 4000 Å is again formed on the surface of the island-shaped active region 1'. At this time, since the isolation oxide 5 is already sufficiently thick, only a small amount of film floating J1 is added. Then the first
Photoresist '-11? for providing the second PN junction as shown in Figure E. i1-oxide5. Ice is poured over the IO, and the oxide film IO on the surface of the active region l' is selectively removed. At this time, at least one side of the edge of the photoresist 11 is again located on the isolation oxide 5 in order to have a large alignment margin. Therefore, when the oxide film 1o is removed again, the isolation oxide 5 is also removed and the shoulder 8 of the island region is exposed again, as shown at 12. Moreover, this time it will be bigger than before. This is because the part close to the isolation oxide 5 is the shoulder S in the previous step.
This is because the exposed part has the same oxide film thickness as the surface, and the oxide film immediately below has almost the same oxide film thickness, so the oxide is removed deeply.

Openings 12 of the oxide films 5 and 10 where vb has been cut in this way
When diffusion is performed to form a second junction from
As shown in FIG. F, the second PN junction 13 bends further at a portion 13' terminating in the isolation oxide 5 and crosses the first PN junction 9, making it impossible to obtain desired characteristics.

As mentioned above, the drawback of the conventional method is that the buried oxide film for isolation is partially removed during the X-etching process. Therefore, the feature of the present invention is to prevent the buried oxide film from being removed excessively. In other words, in order to remove the excess buried oxide film, it is necessary to remove the oxide film on the surface of the island-shaped cow body area.] Since this is a phenomenon that occurs, a PN junction is formed in the island-shaped cow body area. It is characterized by not removing the oxide film on the surface.

In this way, since the surface of the island-like active region is always covered with an oxide film, there is little exposure of "debris" in this region, and therefore the mask size can be adjusted to take full advantage of the advantages of Selfa Line. A conductor device in which the PN junction is terminated with a TPT compound can be obtained with high yield and desired characteristics without causing short-circuit defects in the PN junction.

Next, the present invention will be explained in detail using FIGS. 2 to 4.
When some of the multiple PN junctions terminated in the buried oxide are PN junctions formed between the epitaxial layer and its substrate, and the remaining PN junctions are PN junctions formed by introducing impurities from the outside. An example will be explained. In the following example, impurities are introduced from the outside using the melt Φ-through method 1, but instead, impurities are introduced by ion implantation without exposing the surface of the island-shaped silicon region. Needless to say, it is okay.

In the embodiment shown in FIG. 2, a P-type silicon epitaxial layer 807 is first formed flat on an N silicon substrate 800, and then a thin oxide film 802 and a silicon nitride film 803 are formed.
and are sequentially formed on one surface of the epitaxial layer 807 (
Figure 2A). Here, the thin oxide film 802 is formed by thermal oxidation.
It is appropriate to deposit the silicon nitride film 803 to a thickness of 15 UOX by a thermal reaction of monosilane and ammonia. Next, the silicon nitride film 803 and the oxide film 802 are selectively etched in sequence.
Furthermore, using the remaining silicon nitride film 803 and oxide film 802 as a mask, the exposed portion of the P-type epitaxial layer 807 is etched to cover more than half the thickness of the epitaxial layer (FIG. 2B).

Next, thermal oxidation is performed using the remaining silicon layer M803 as a mask to selectively form a thick oxide film 801. At this time, the surface of the selective oxide film 801 is made to be the same as the surface of the ZOE l〇-bitaxial@807. In addition, when silicon is converted into a silicon oxide film by thermal oxidation, the thickness of the silicon film is approximately half the thickness of the silicon oxide film, so at the end of this process, P
A selective oxide film 801 is formed through the silicon epitaxial layer 807, so that the PN junction between the epitaxial layer 807 and the substrate 800 is terminated at this thick oxide film 801 (FIG. 2C). ).

Next, residual silicon nitride 803 adhering to the surface
Then, the silicon oxide film 802 that appeared on the surface is grown to a thickness of approximately 3000 nm, and this thick silicon oxide film 820 is used to form a P-type silicon epitaxial layer 807.
(Figure 2 D).

Next, a photoresist film 808 is selectively deposited, and using this photoresist M808 as a mask, the silicone film 820 on the P-type silicon epitaxial layer 807 is selectively etched in areas other than those where impurities are planned to be introduced. is 821 with a thickness of about 50 OA (Fig. 2 E
).

Next, the photoresist film 808 on the surface is removed. .

When thermal diffusion is performed, the silicon oxide film on the surface 821°82
0 converts to the linker layer 830. At this time, 500X
All of the thin silicon oxide film 821 is a phosphorus glass layer 830.
However, since the silicon oxide film is thick in the other portion 820, the silicon oxide film is not entirely converted into a phosphor glass layer and is formed only on the surface. Roughly, when the heat treatment is continued, phosphorus atoms are diffused into the P-type silicon epitaxial layer 1807 in the portion where the phosphor glass layer 830 is in contact with the P-type silicon epitaxial layer 807, and the N-type region 8
10 is formed (FIG. 2F).

Next, the link glass layer 830 formed on the surface is removed,
The surface is covered with a silicon oxide film 831 by thermal oxidation again (FIG. 2G).

Openings selectively reaching the silicon layer are provided in the silicon oxide [831] covering the surface (FIG. 2H).

Metal thin films 840 and 841 are selectively formed covering these openings to serve as electrodes for the PfIM region, i.e., the source region 807 and the N-type region, i.e., the emitter region 810 (second ν
II). Contact to the collector region 800 is provided at another suitable location. Next, in the embodiment of FIG. 3, a photoresist film 908 is selectively deposited after the step of FIG. Then, the remaining silicon complex [803] is partially etched to expose the thin oxide film 802 with a thickness of 500 Å thereunder (FIG. 3A). Here, if the silicon nitride film is etched by plasma etching in a Freon atmosphere, the difference in etching speed between the silicon nitride film and the silicon oxide film makes it possible to leave the silicon oxide film in a well-controlled manner. When the photoresist film 908 is removed and phosphorus is thermally diffused, the silicon oxide films 801 and 802 are converted into a phosphorus glass layer 903, and all of the exposed thin silicon oxide films 802 become phosphorus glass layers. 903, but other parts are formed only on the surface. When heat treatment is further continued, the linker glass layer 903 becomes P
In the portion in contact with the type epitaxial layer 807, phosphorus atoms are diffused into the P type epitaxial layer 13-807, forming an Nfi region 810 (FIG. 3B). Next, the link glass layer 903 formed on the surface is removed, and the Nff1 region 810 is covered with a silicon oxide film by thermal oxidation, and the remaining silicon enhancement film 8038 is removed by writing Freon plasma etching. The same structure as G is obtained, and the steps similar to those in FIG. 2 H and I are performed.

Next, in the embodiment shown in FIG. 4, after the step shown in FIG. The silicone film 803 is partially etched in Freon plasma to reduce the film thickness below it to 50%.
0's thin oxide film 802 is exposed to the surface (Fig. 4A) C1
Next, the photoresist film 918 on the surface is removed, and then thermal oxidation is performed to grow an oxide film 920 of 300 OA in the area where the silicon nitride film was removed (FIG. 4B). next,
The remaining silicon nitride film 803 is removed and the film thickness below it is reduced to 50
A thin 14-oxide film 802 is exposed to the surface (FIG. 4C).

Next, when thermal diffusion of phosphorus is performed, the silicon oxide film is converted into a phosphorus glass layer 913, and the 500% that appeared on the surface of the previous process is
The thin silicon oxide film 802 of A is entirely a phosphorus glass layer 91
3, but the other portions 920 and 801 are formed only on the surface. When the heat treatment is performed in succession, phosphorus atoms are diffused into the P-type epitaxial layer 807 in the portion where the phosphor glass layer 913 is in contact with the P-type epitaxial layer 807, and an N-type region 810 is formed (FIG. 4D). )
.

Next, the link glass layer 913 formed on the surface is removed, and the hemiform region 8]0 is covered with a silicon oxide film by thermal oxidation to obtain the same structure as shown in FIG. 2G. It is recommended that you follow the same steps as in Figure 2 H and I below.

In the embodiments shown in FIGS. 2 to 4, a method for manufacturing an NPN transistor has been described, but it goes without saying that a PNP transistor can also be manufactured using the same .mu. method by changing the impurity or conductivity type. Also, washed emitters are used in speed transistors.
ter ) structure, and can also be applied to manufacturing not only transistors but also diodes and integrated circuit devices including these.

As explained above, according to the present invention, since the buried silicon oxide film is not removed excessively, manufacturing is easy, and the yield can be expected to be improved without sacrificing the performance of the device. big O

[Brief explanation of drawings]

Figures 1A-F are cross-sectional views of the main manufacturing steps of the conventional manufacturing method to explain the drawbacks of the conventional method, Figures 2A-F, and Figure 3A
-B and FIGS. 4A to 4D are cross-sectional views of the main manufacturing steps of the method of manufacturing a semiconductor device according to an embodiment of the present invention. 800...N-type silicon substrate, 807.
・・・・・・Pm silicon epitaxial layer, 80
1, 802.820.831.920・・・・・・・・・
・Silicon oxide film, 803...Silicon nitride film, 808, 908.918...Photoresist, film, 8]0......N Mold area, 840.841 ...... Gold Nm1t pole, 8
30.903.913・・・・・・・・・Link glass layer〇171

Claims (1)

[Claims] 1. At least two P atoms in a semiconductor region surrounded by a relatively thick oxide selectively buried in the entire surface of a semiconductor substrate.
a structure in which N junctions terminate on the same side of the thick oxide;
In the method for manufacturing a semiconductor device, one of the PN junctions is formed between a semiconductor substrate and an epitaxially grown film formed on the semiconductor substrate, and the other PN junction is formed without exposing the surface of the semiconductor region. A method of manufacturing a semiconductor device, characterized in that the semiconductor device is formed by introducing impurities from the outside. λ Of the two PN junctions that terminate on the same side of the thick oxide of the semiconductor region surrounded by the thick modified material, one PN junction formed by introducing impurities from the outside is an insulator that covers the surface of the semiconductor region. Claim 1 characterized in that the thin skin region is completely converted into a crow layer by heat treatment in a scum containing impurities, and the impurity is diffused from the crow layer into the semiconductor region. A method for manufacturing a semiconductor device according to paragraph 1.