JPS58107676A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance electric conductivity and make it possible to perform high withstand voltage operation by determining a thin part and a thick part of a gate insulating film, respectively, by a self-aligning method, thereby eliminating unstable elements in manufacturing processes. CONSTITUTION:Source and drain electrode diffused layers 12 and 13 are formed by impurities, whose conducting type is reverse with respect to that of a substrate, in the semiconductor substrate 11. The thin part 14 of the gate insulating film is located between the source and drain electrodes 12 and 13. A first layer polycrystalline silicon electrode 15 is located thereon, and an insulating film 16 is located thereon. A hole 17 is provided at a part thereof, and a second polycrystalline silicon layer 18 is formed thereon. Said polycrystalline silicon 18 completely covers the first layer polycrystalline silicon 15. The same impurities are introduced into the first layer polycrystalline silicon 15 and the second layer polycrystalline silicon 18 and they are electrically shorted through the hole 17.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MO8MP conductor using polycrystalline silicon as a gate electrode.

As a semiconductor device, in a silicon gate MO8) transistor, the source and drain are formed as a gate polycrystalline silicon disk, so the overlap between the gate electrode and the source and drain diffusion layer is reduced.

Conventionally, in a MOS (MOS) transistor, increasing the withstand voltage of the drain increases the operational margin of the transistor and expands the range of applications of such iron content. And now programmable ROM (R@ad
0nly g@mory) [FROM] uses two layers of polycrystalline silicon to construct a %ROM cell, and by injecting charge into electrically floating electrodes, the cell is constantly maintained. It is well known that a cell creates an ON state, and as a whole, an ON transistor and an OFF transistor are created to form a ROM.

In such a FROMK, normal operation is performed with a power supply of 5 V, but when programming by injection operation, a high voltage t- is applied. Therefore, it is necessary to form a transistor that can operate by applying this high voltage and a transistor that can operate at a low voltage on the same substrate. Having a transistor that can operate at high voltages and a transistor that can operate at low voltages on the same substrate greatly expands the range of applications for the device, and is useful not only for FROM but also for a wide range of general applications. It can also be used for devices.

Conventionally, a transistor capable of such high-voltage operation was conceived by increasing the thickness of the gate insulating film in the MO8 structure to provide a withstand voltage for the drain voltage9. The breakdown voltage of the drain depends on the thickness of the gate insulating film; the thinner the gate insulating film, the lower the breakdown voltage, and the thicker the gate insulation film, the higher the breakdown voltage. The purpose here is to increase the withstand voltage, but it is not an extremely high withstand voltage. Normally, if the gate insulating film thickness is 5ooXs degrees, the withstand voltage is about 20V, and if the gate insulating film is 100OA, the withstand voltage is about 25V. , the purpose is to configure the drain breakdown voltage with two or more types of transistors in the same substrate at these operating voltages.

Next, the structure of a conventional transistor is shown in FIG.

In the substrate 1, there are a source electrode diffusion layer 2 and a drain electrode diffusion layer 3, between which a thick part 4 and a thin part 5 of a gate insulating film are formed, and a gate/polycrystalline silicon 6 is formed thereon. However, in this transistor, the gate insulating film on the drain/source side is thicker, and the central part is thinner. In the t-L9 transistor with this structure, the gate insulating film is partially thick between the drain electrode and the gate electrode, so the electric field strength between them is reduced, and the curvature of the depletion layer is reduced. (This transistor operates at a high voltage.)

becomes possible. If the gate insulating film is thick, the drain breakdown voltage increases for the above reason.

As the gate insulating film becomes thicker, the conductivity of the transistor deteriorates, and the size of the transistor must be increased to maintain a specified current tolerance. This is disadvantageous for integrated circuits. Therefore, the conventional technique shown in FIG. 1 improves the conductivity and enables high breakdown voltage operation by partially thinning the gate insulating film.

In this conventional example, in order to create a thick film and a thin film in a predetermined gate insulating film region, a thick film is first formed, a part of which is removed, and a thin H layer is grown. Because the process of removing the film is involved in positioning the area,
Depending on the method used for its removal, regions of the thick film could change, resulting in unstable properties.

The present invention has a structure that does not have such disadvantages.

The present invention has a structure in which the thin and thick parts of the gate insulating film are determined by gate electrodes in a self-aligned manner, eliminating unstable factors in the manufacturing process, and increasing electrical conductivity. The present invention provides a semiconductor device capable of voltage-resistant operation.

The structure of the present invention is shown in FIG. Source/drain electrode diffusion layers 1 & 13 are formed in the semiconductor substrate 11 with impurities having conductivity opposite to that of the substrate, and a thin gate insulating film 14 is located between the source/drain electrodes. There is a first layer of polycrystalline silicon electrode 15, and an insulating film 16 is further above it, and a hole 17 is provided in a part of it, and a second layer of polycrystalline silicon 1 is further above it.
8, and this polycrystalline silicon layer 18 completely covers the first layer of polycrystalline silicon 15. The same impurity is introduced into the first layer of polycrystalline silicon 15 and the second layer of polycrystalline silicon, and they are electrically short-circuited through the hole 17.

In this structure, the gate insulating film 19.20 facing the source 1λ drain 1311 is covered by the gate electrode of the second layer of polycrystalline silicon 18, and the diffusion layer of the source 1λ drain 13 is self-aligned. It is formed as follows. Therefore,
Since the gate insulating film 20 between the drain 13 and the gate polycrystalline silicon electrode 18 is thick, the electric field strength between the two electrodes is weakened, so that the gate insulation between the depletion layer substrate 11 and the drain 13 is reduced. The curvature at the interface near the film 20 becomes gentler, and the drain breakdown voltage, which is the limit electric field strength, is increased. Therefore, high voltage operation is possible.

Further, the gate insulating film 1 below the first polycrystalline silicon 15
Since No. 4 is thinner, the electrical conductivity is improved, and the desired MOS transistor with high withstand voltage and improved electrical conductivity is obtained.

First layer polycrystalline silicon 15 and second layer polycrystalline silicon 1
8 and has the same potential, and has the same function as the gate electrode. Therefore, a thin gate insulating film and a thick gate insulating film exist under this electrode, and the same effect as the conventional technique shown in FIG. 1 can be obtained. In the structure of H, the thin gate insulating film is determined by the first layer of polycrystalline silicon, and the thick insulating film is determined by the second layer of polycrystalline silicon. Note that the area of the thick insulating film is determined by the amount of the first layer of polycrystalline silicon remaining, but whether the polycrystalline silicon is left or removed during the manufacturing process During the process, the first layer polycrystalline silicon tends to become smaller and the region of the thick insulating film becomes larger, so that the breakdown voltage does not become unstable during the manufacturing process. Therefore, through the manufacturing process, a device with high breakdown voltage operation and good electrical conductivity can be obtained without affecting the breakdown voltage of the device.

Next, in FIG. 2, since a thick gate insulating film is provided also in the source IIIK, the electrical conductivity as a transistor is not very good. Therefore, a structure shown in FIG. 3 may also be considered.

An explanation will be added in FIG. 3, but the numbers in the figure are the same as in FIG. 2. In the substrate 11, there are nine sources, one λ, and one drain 13, which are made of impurities of conductivity type opposite to that of the substrate. The structure on the drain side is the same as that in FIG. 2, but the source 121 [
In 1, the second layer polycrystalline silicon 1
8, the interlayer insulating film 16 is determined in a self-aligned manner, and then the first
The layer of polycrystalline silicon 15 is also determined in a self-aligned manner so that no thick insulating film is left on the source 12 side, and the second layer of polycrystalline silicon 18 is not covered more than the first layer of polycrystalline silicon 15. It's K. By doing this, the thin insulating film faces the source side, making it possible to obtain a high breakdown voltage device with improved electrical conductivity compared to the case of FIG. 2, which had a thick insulating film. Even in this case, the meaning of the embodiment of the invention shown in FIG. 2 is the same.

Next, FIG. 4 shows an embodiment for manufacturing such a high voltage transistor of the present invention. This embodiment is based on the above-mentioned FR
Let us now discuss the case of configuring OM.

For example, a field oxide film 32 is formed on a P-type silicon substrate 31 by a normal selective oxidation method, and a relatively thin silicon oxide film 33 is formed as a gate insulating film 1-1.
A layer of polycrystalline silicon is grown, and impurities such as phosphorus are introduced into the polycrystalline silicon to make it N-type. After that, the first layer polycrystalline silicon 34 is left in a predetermined place [Fig. 4 (
a)].

Next, the surface of the first layer of polycrystalline silicon is oxidized to grow an oxide film 35t, and the first layer of polycrystalline silicon 34 is grown.
Due to this oxidation, the remaining gate oxide film 33 is
It grows further to become a thick gate oxide film 36. and,
A suitable hole is opened in a portion 38 of the thick gate oxide film 36 in order to conduct wiring from a portion 37 on the first layer polycrystalline silicon or a direct diffusion region of polycrystalline silicon. after that,
Polycrystalline silicon is grown again, and photoresist is applied as an upper layer (39f): Buttering is performed to leave the second layer of polycrystalline silicon 40 in a predetermined location.

Then, this photoresist 39 is masked and patterned with 40t of second layer polycrystalline silicon [Fig. 4(b)].
.

Next, photoresist 39. The second layer of polycrystalline silicon 40t is removed as a mask and the interlayer insulating film 35t is removed, and the first layer of polycrystalline silicon is further removed.

Further, the thick gate oxide film 36t is removed. Thereafter, using, for example, an ion implantation method or a hot vapor phase diffusion method, a source is applied to the second layer of polycrystalline silicon 40 in a self-aligned manner.
A drain diffusion layer 41t is formed [FIG. 4(C)]. At this time, impurities are also introduced into the #I second layer of polycrystalline silicon, which appears as an N-type electrode.

Next, an insulating film 42t such as phosphor glass is grown by vapor phase growth, holes are provided at predetermined locations, and metal wiring 43 is formed (FIG. 4(d)). .

In this way, the transistor on the left in Figure 4 is the high voltage transistor of the present invention, and the transistor in the center is insulated between the first layer of polycrystalline silicon and the second layer of polycrystalline silicon. They are separated by a membrane and constitute a FROM memory cell/transistor. The transistor on the right has a thicker gate insulating film and has a higher breakdown voltage, but has poor electrical conductivity.

In this transistor, the wiring portion provided at the hole 38 is formed at the same time as the hole 37 is provided for electrically shorting the first layer of polycrystalline silicon and the second layer of polycrystalline silicon. Open a hole and directly connect the diffusion layer and polycrystalline silicon matrix.
Connection is now possible. Here, when configuring a transistor with good electrical conductivity, that is, a normal transistor with low breakdown voltage using a relatively thin gate oxide film, in the cell transistor in the center part of FIG. It is sufficient to provide a hole that directly connects the polycrystalline silicon layer and the second layer polycrystalline silicon. At this time, the second layer of polycrystalline silicon and the first layer of polycrystalline silicon are positioned in a self-aligned manner and patterned to have the same width. Therefore, the gate oxide film of this transistor is made of a relatively thin film, resulting in a transistor with reduced conductivity.

The transistor of the present invention is a nine transistor shown on the left side of FIG.
This is a transistor that covers a layer of polycrystalline silicon, uses the same potential and electrodes, and has a thick gate insulating film for high breakdown voltage and a thin gate insulating film for high conductivity. be.

Although the FROMO manufacturing method has been explained here, this device can be applied to any device that uses two layers of polycrystalline silicon, and can be used in a wide range of applications, such as using the second layer of polycrystalline silicon for wiring. , it is also possible to use a single transistor in the manufacturing method shown in this example. )

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the structure of a conventional semiconductor device.
The figure is a structural cross-sectional view of a semiconductor device according to an embodiment of the present invention,
FIG. 3 is a cross-sectional view of the structure of the semiconductor device shown in FIG. 2, and FIGS. It is a diagram. In the figure, 1, 11.31... semiconductor substrate, λ3.1 & 13.41... source/drain diffusion layer, 4.19, 20.36... thick Gate insulating film, 5.14°33... Thin gate insulating film, 6... Gate polycrystalline silicon, 1&34.
...First layer gate polycrystalline silicon, 18.40.
...Second layer gate polycrystalline silicon, 16.35
...It is an interlayer insulating film. 1 Old S f D

Claims (1)

[Scope of Claims] A source and drain region of a second conductive layer provided on a first conductive substrate, and a thin gate insulator and a thick gate insulator provided on the surface of the semiconductor substrate between the source and drain regions. With the genus. a large first polycrystalline silicon gate electrode provided on the thin gate insulating layer; an insulating film covering the first polycrystalline silicon gate electrode; provided on the thick gate insulating layer;
a second polycrystalline silicon gate electrode in contact with the insulating film, connected to the first polycrystalline silicon gate electrode, and having a self-aligned positional relationship with at least the train region; semiconductor device.