JPH0378244A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0378244A JPH0378244A JP21525489A JP21525489A JPH0378244A JP H0378244 A JPH0378244 A JP H0378244A JP 21525489 A JP21525489 A JP 21525489A JP 21525489 A JP21525489 A JP 21525489A JP H0378244 A JPH0378244 A JP H0378244A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- oxide film
- wiring
- type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000008018 melting Effects 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 abstract 2
- 239000011229 interlayer Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路に関し、特にＭＯ５型トラン
ジスタにおけるコンタクト方法の改良に係るものでちる
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to improvements in the contact method for MO5 type transistors.
第２図は従来のＮチャネルトランジスタのパターン図を
示す。FIG. 2 shows a pattern diagram of a conventional N-channel transistor.
Ｐ型半導体基板上てフィールド分Ｓ＊化膜ｆｌ）、ゲー
ト酸化膜及びゲート電極（２）を形成し、選択された領
域に各々Ｎ型不純物、Ｐ型不純物をイオン注入し、熱処
理を行ないＮ十拡散層（５）及びＰ十拡散層（６）を形
成している。次に、酸化膜を眉間膜としてデポし、しか
るのちにコンタクト（３）をエツチングにより開孔して
いる。この時、Ｎ十拡散層（５）及びＰ十拡散層（６）
への開孔は数個、ゲート電極へのコンタクトは１個で、
ある。A field S* film (fl), a gate oxide film, and a gate electrode (2) are formed on a P-type semiconductor substrate, and N-type impurities and P-type impurities are ion-implanted into selected regions, respectively, and heat treatment is performed to form N-type impurities. A ten diffusion layer (5) and a P ten diffusion layer (6) are formed. Next, an oxide film is deposited as a glabellar film, and then contacts (3) are opened by etching. At this time, the N10 diffusion layer (5) and the P10 diffusion layer (6)
There are several openings to the gate electrode and one contact to the gate electrode.
be.
最後に、スパッタ法によシＡｌ膜を被着した後ＲＩＥに
よりエツチングし、Ａｌ配線（４）を形成しＮ十拡散層
（６）とＡｌ配線（４）及びゲート電極（２）とＡｌ配
線（４）を接続していた。Finally, after depositing an Al film by sputtering, etching is performed by RIE to form an Al wiring (4), connecting an N diffusion layer (6), an Al wiring (4), a gate electrode (2), and an Al wiring. (4) was connected.
従来の半導体装置は以上のように構成されていたので、
ゲート電極へのコンタクトの開孔が不十分な場合、又は
Ａｌ配線とダート電極との密着性が不十分な場合、１ケ
所のコンタクト開孔では電圧がゲート電極に伝わらない
などの問題点があった。Since conventional semiconductor devices were configured as described above,
If the contact hole to the gate electrode is insufficient, or if the adhesion between the Al wiring and the dirt electrode is insufficient, there may be problems such as voltage not being transmitted to the gate electrode with a single contact hole. Ta.
この発明は上記のような問題点を解消するためになされ
たもので、安定してゲート電極とのコンタクトがとれる
半導体装置を得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device that can stably make contact with a gate electrode.
この発明に係る半導体装置は、ゲート電極とＡｌ配線の
コンタクトを複数個設けたものである。A semiconductor device according to the present invention is provided with a plurality of contacts between a gate electrode and an Al wiring.
この発明におけるゲート電極とＡ４配線のコンタクトを
複数個設けたので、１カ所のコンタクトに“開孔不良”
などの問題点が生じても他のコンタクトに！、ｊ７Ａｌ
配線とゲート電極のコンタクトが可能になυ、安定した
コンタクトが取れ、歩留シ向上に寄与する。Since multiple contacts are provided between the gate electrode and the A4 wiring in this invention, "opening defect" occurs in one contact.
If any problems arise, please contact other contacts! ,j7Al
This enables contact between the wiring and the gate electrode, allowing for stable contact and contributing to improved yields.
以下、この発明の一実施例を図について説明する０
第１図はこの発明の一実施例によるＮチャネルトランジ
スタのパターン図を示す。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a pattern diagram of an N-channel transistor according to an embodiment of the present invention.
Ｐ型半導体基板上にフィールド分離酸化膜＋１１、ゲー
ト酸化膜及びゲート電極（２）を形成し、選択された領
域に各々Ｎ型不純物、Ｐ型不純物をイオン注入し、熱処
理を行ない、Ｎ十拡散層（５）及びＰ＋拡散層（６）を
形成している。次に、酸化膜を眉間膜としてデボし、し
かるのちにコンタクト（３）をエツチングによシ開孔し
ている。この時、ゲート電極へのコンタクトを２力所以
上の複数個取る。A field isolation oxide film +11, a gate oxide film, and a gate electrode (2) are formed on a P-type semiconductor substrate, and N-type impurities and P-type impurities are ion-implanted into selected regions, respectively, and heat treatment is performed to increase N+ diffusion. A layer (5) and a P+ diffusion layer (6) are formed. Next, the oxide film is debossed as a glabellar film, and then a contact (3) is opened by etching. At this time, a plurality of contacts with two or more force points are made to the gate electrode.
最後に、スパッタ法によシＡｌ膜を被着した後、ＲＩＥ
によりエツチングし、Ａｌ配線（４）及びゲート電極（
２）とＡｌ配線（４）を接続する。Finally, after depositing an Al film by sputtering, RIE
Al wiring (4) and gate electrode (
2) and the Al wiring (4) are connected.
なお、上記実施例ではＮチャネルトランジスタに適用し
た場合を示したが、Ｐチャネルトランジスタにも適用す
ることができる。Note that although the above embodiment shows the case where the present invention is applied to an N-channel transistor, the present invention can also be applied to a P-channel transistor.
以上のようにこの発明によれば、２工程のパターン改定
のみで改善されるので、安価に製造できるという効果が
ある。As described above, according to the present invention, the improvement can be achieved by only modifying the pattern in two steps, so there is an effect that manufacturing can be carried out at low cost.
第１図はこの発明の一実施例によるＮチャネルトランジ
スタを示すパターンレイアクト図、第２図は従来のＮチ
ャネルトランジスタを示すパターンレイアクト図である
。
図において、（１）はフィールド分離酸化膜、（２）は
ゲート電極、（３）はコンタクト、（４）はＡｌ配線、
（６）はＮ十拡散層、（６）はＰ＋拡散層を示す。なお
、図中、同一符号は同一 または相当部分を示す。
第１図FIG. 1 is a pattern layout diagram showing an N-channel transistor according to an embodiment of the present invention, and FIG. 2 is a pattern layout diagram showing a conventional N-channel transistor. In the figure, (1) is a field isolation oxide film, (2) is a gate electrode, (3) is a contact, (4) is an Al wiring,
(6) shows an N+ diffusion layer, and (6) shows a P+ diffusion layer. In addition, the same symbols in the figures indicate the same or equivalent parts. Figure 1
Claims (1)
極を有する半導体装置において、前記ゲート電極と電源
及び配線として用いられたＡｌ薄膜と電気的接続部を形
成する場合、前記電気的接続部を複数個設けたことを特
徴とする半導体装置。In a semiconductor device having a gate electrode formed of polycrystalline silicon or a high melting point metal, when forming an electrical connection between the gate electrode and an Al thin film used as a power supply and wiring, a plurality of electrical connections are formed. A semiconductor device characterized in that a semiconductor device is provided with a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21525489A JPH0378244A (en) | 1989-08-21 | 1989-08-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21525489A JPH0378244A (en) | 1989-08-21 | 1989-08-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0378244A true JPH0378244A (en) | 1991-04-03 |
Family
ID=16669272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21525489A Pending JPH0378244A (en) | 1989-08-21 | 1989-08-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0378244A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5853646A (en) * | 1994-05-11 | 1998-12-29 | Daikin Industries, Ltd. | Molding method and dilution agent for mold releasing agent |
| KR20130088151A (en) | 2010-09-13 | 2013-08-07 | 유니마테크 가부시키가이샤 | Fluorine-containing copolymer |
| KR20190132417A (en) | 2017-03-22 | 2019-11-27 | 유니마테크 가부시키가이샤 | Polyfluoroalkyl phosphate esters or salts thereof and release agents containing them as active ingredients |
-
1989
- 1989-08-21 JP JP21525489A patent/JPH0378244A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5853646A (en) * | 1994-05-11 | 1998-12-29 | Daikin Industries, Ltd. | Molding method and dilution agent for mold releasing agent |
| KR20130088151A (en) | 2010-09-13 | 2013-08-07 | 유니마테크 가부시키가이샤 | Fluorine-containing copolymer |
| KR20190132417A (en) | 2017-03-22 | 2019-11-27 | 유니마테크 가부시키가이샤 | Polyfluoroalkyl phosphate esters or salts thereof and release agents containing them as active ingredients |
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