JPS58107628A - Loquid phase epitaxial growth method - Google Patents
Loquid phase epitaxial growth methodInfo
- Publication number
- JPS58107628A JPS58107628A JP56206563A JP20656381A JPS58107628A JP S58107628 A JPS58107628 A JP S58107628A JP 56206563 A JP56206563 A JP 56206563A JP 20656381 A JP20656381 A JP 20656381A JP S58107628 A JPS58107628 A JP S58107628A
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- inp
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- grown
- liquid phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02392—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02461—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02625—Liquid deposition using melted materials
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Light Receiving Elements (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、 ＩｎＰ基板上にＩｎ、−、ＧａｇＡｓ、
Ｉｔｓ、４ＧａｍＡｓ Ｐ、 及びＩ ｎ Ｐ／等
のエピタキシャル結晶−ｙ
層を多層成長する液相エピタキシャル（ＬＰＦｉ ）成
長方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides In, -, GagAs,
The present invention relates to a liquid phase epitaxial (LPFi) growth method for growing multiple layers of epitaxial crystals such as Its, 4GamAs P, and InP.
化合物半導体の多層液相エピタキシャル成長は光通信用
発光・受光素子である。半導体レーザ（以下ＬＤと呼ぶ
）１発光ダイオード（以下ＬＥ／と呼ぶ）、アバランシ
・フォトダイオード（以下ＡＰＤと呼ぶ）、フォトダイ
オード（以下ＦＤと呼ぶ）等の素子を得る丸めの重要な
結晶成長方法であシ。Multilayer liquid-phase epitaxial growth of compound semiconductors is used for light-emitting and light-receiving devices for optical communications. An important crystal growth method for rounding to obtain devices such as semiconductor lasers (hereinafter referred to as LDs), light emitting diodes (hereinafter referred to as LE/), avalanche photodiodes (hereinafter referred to as APDs), and photodiodes (hereinafter referred to as FDs). Adashi.
欠陥の少ない高品質な成長結晶層が得られる成長方法の
確立がｉＩすれている。現在、光通信用発光素子として
は発振波長が０．８から１．６μｍ域のＧａＡｓ−Ｇａ
ＡｔＡｓ系あるいはＩｎＰ−ＩｎＧａＡｓＰ系のＬＤ及
びＬＥＤの研究開発が主流である。We are about to establish a growth method that can provide a high-quality grown crystal layer with few defects. Currently, GaAs-Ga with an oscillation wavelength in the 0.8 to 1.6 μm range is used as a light emitting device for optical communication.
Research and development of AtAs-based or InP-InGaAsP-based LDs and LEDs is the mainstream.
また、 ＧａＡｓ−ＧａＡｔＡｓ系のＬＤ及びＬＥＤの
主な発振波長０．８μｍ〜０．８７μｍに対する光検出
器としては８ｉ単結晶を用いたＰＤあるいはＡＰＤが広
く実用されている。しかしながら８ｉ単結晶で社１μｍ
波長以上の光を検出することは吸収係数が小さくなるた
めに実用上作製困難であや、光ファイバーの伝送損失の
低い１．１μｍ〜１．６μｍ波長域では使用することが
できない。また、１．１μｍ以上１．５μｍ波長域用と
してはＧｅ−ＡＰＤがあるが暗電流と過剰雑音の点で必
ずしも光通信用として最適な光検出器ではない、このた
め璽−Ｖ族化合物半導体等によるＦＤあるいはＡＰＤが
要求されておｊ）、 ＩｎＧａＡｓ、 ＩｎＧａＡｓ
Ｐ、 ＧａＡｊ８ｂｅＱａ ＡｔＡ３Ｓｂ、 Ｇａ ８
ｂ等による試作報告例がある。Furthermore, PDs or APDs using 8i single crystals are widely used as photodetectors for the main oscillation wavelengths of 0.8 μm to 0.87 μm of GaAs-GaAtAs LDs and LEDs. However, with 8i single crystal, the thickness is 1 μm.
It is practically difficult to detect light of a wavelength longer than that due to the small absorption coefficient, and it cannot be used in the wavelength range of 1.1 μm to 1.6 μm, where the transmission loss of optical fibers is low. In addition, Ge-APD is available for use in the 1.1 μm to 1.5 μm wavelength range, but it is not necessarily the best photodetector for optical communications due to dark current and excessive noise. InGaAs, InGaAs
P, GaAj8beQa AtA3Sb, Ga 8
There are examples of prototypes reported by B.
第１図はＩｎ、、、、、Ｇａ、Ａｓ、Ｐ、−、層を光吸
収層として。In Fig. 1, layers of In, ..., Ga, As, P, - are used as light absorption layers.
ＩｎＰ中Ｋｐｎ接合を形成したプレーナＩ！ＡＰＤの報
告例であり、特願昭５４−３９１６９にくわしく述べら
れている。この構造のウェーハの形状としては、ｎＩｎ
Ｐ基板ｌｌ上ＫＪ−ＩｎＰバッファ一層１２を形成し１
次Ｋ ｎ Ｍ Ｉ ｎ ｔ −ｘ Ｇａ ” Ａ Ｉｙ
Ｐ ｔ−ｙ層（光吸収層）１３を形成した後、ｎ型Ｉ
ｎＰ層１４を形成したウーー４であシ、とのウー−／’
Ｋ基本的には選択拡散によ１ｆ領域１５をＩｎＰ層１
層中４中成するととＫよシ低晴電流、高増倍特性のＡＰ
Ｄが得られている。これと同様な素子構造をＩｎＰと格
子整合するＩ ｎ ｔ −ｍ Ｇａ ” Ａ ｓｙ Ｐ
ｓ−ｙの最長波長組成に相当するＩｎｌ−１ＧａｊＡ
ｓを光吸収層として、 Ｉｎ、、Ｇａ１ＡｓｙＰ、−
、を活性層とするＬＤあるいはＬＥＤ等の光源からの光
の全波長光を検出するＡＰＤ、ＦＤ等を作製する場合Ｋ
Ｆｉ、 Ｉｎ、−。Planar I with Kpn junction formed in InP! This is a reported example of APD, and is described in detail in Japanese Patent Application No. 54-39169. The shape of the wafer with this structure is nIn
A KJ-InP buffer layer 12 is formed on the P substrate 1.
NextK n M I n t −x Ga ” A Iy
After forming the Pty layer (light absorption layer) 13, the n-type I
The nP layer 14 was formed using the U-4 and the U-/'
Basically, the 1f region 15 is formed into the InP layer 1 by selective diffusion.
When the 4th layer is formed, the AP has low current and high multiplication characteristics
D is obtained. A device structure similar to this is lattice matched with InP.
Inl-1GajA corresponding to the longest wavelength composition of s-y
s as a light absorption layer, In,, Ga1AsyP, -
, when producing an APD, FD, etc. that detects all wavelengths of light from a light source such as an LD or LED with K as an active layer.
Fi, In, -.
Ｇａ５ＡＳ上ＫＩｎＰ層をエピタキシャル成長する必要
がある。しかしながら液相成長方法においては。It is necessary to epitaxially grow a KInP layer on Ga5AS. However, in liquid phase growth methods.
Ｉｎ１−ｊＧａ、 Ａｓ上ＫＩｎＰを成長しようとする
とＩｎＰ成長用溶液に逆Ｋ Ｉｎ、−、Ｇａｓ Ａｓ層
が溶けてしまうといういわゆるメルトバーク現象が生じ
多層構造ができない、このためＩｎ、、 Ｇａｓ Ａｓ
上にいわゆるアンチ・メルトバックＩｎ、ＪＩＧａｓ
ＡｓｙＰ、−、層をエピタキシャル成長後ＩｎＰ層を成
長するととＫよ抄着構造が得られている。この場合にお
いてもＩｎ、−。When trying to grow KInP on In1-jGa,As, a so-called melt bark phenomenon occurs in which the reverse KIn,-,GasAs layer dissolves in the InP growth solution, and a multilayer structure cannot be formed.For this reason, In,,GasAs
Above is the so-called anti-meltback In, JIGas
When an InP layer is grown after epitaxially growing an AsyP layer, a K-shaped structure is obtained. Also in this case, In, -.
Ｇａ１ＡｓとＩ ｎ Ｉ−ｓ Ｇａ ” Ａ”ｖ Ｐ＋
−ｙ界面を良好な鏡面にする九めにアンチ・メルトバッ
クＩｎ、−、Ｇａ５Ａ５ｙＰ、−７の組成として１≧０
．２４．ｙ層０．５５程度が必要であシ、これＫついて
は特願１＠ ５６−１０９６９０にくわしく述べである
。またＩｎ、、ＧａｍＡｓを光吸収層として１．０μｍ
以上の厚膜成長した上記同様構造の４ＦＤ用ウエーハあ
るいは光源としてのＬ１１！ｉＤ用として２μｍ程度の
厚膜Ｉｎ、−、ＧａｇＡａ、Ｐ、−。Ga1As and I n I-s Ga ” A”v P+
- To make the y interface a good mirror surface, the composition of anti-meltback In, -, Ga5A5yP, -7 is 1≧0.
．． 24. A y layer of about 0.55 is required, and this K is described in detail in Japanese Patent Application No. 1@56-109690. In addition, a light absorption layer of In, GamAs with a thickness of 1.0 μm
L11 as a wafer for 4FD or a light source with the same structure as above with the above thick film grown! A thick film of about 2 μm In, -, GagAa, P, - for iD.
層を活性層として上記Ｉｎ１−、 Ｇａ、 ＡｓｙＰ、
−ｙ層上に結晶層が得られるがウェーハの周縁領域では
ミスフィツト転位が導入され、極端な場合Ｋｄヘテロな
層構造をｌさないことがある。第２図、第３図にそれを
説明するための概略図をＩｎ、−、Ｇａ、Ａｓを光吸収
層とするＡＰＤ用ウェーへの作製例をもとに組明する。The above In1-, Ga, AsyP,
Although a crystalline layer is obtained on the -y layer, misfit dislocations are introduced in the peripheral region of the wafer, and in extreme cases, a Kd heterolayer structure may not be formed. FIG. 2 and FIG. 3 are schematic diagrams for explaining this, based on an example of fabricating an APD wafer having a light absorption layer of In, -, Ga, and As.
第２図ｈ’ｔＩ”型、Ｉｎｋ（１００）基板２１上にｎ
＋−ＩｎＰ ２２をＬＰＩ威長後、成長温度で格子整合
条件し満足するようＫｎ型Ｉｎ、。Figure 2 h'tI'' type, n on Ink (100) substrate 21
After LPI growth of +-InP 22, Kn-type In is grown to satisfy lattice matching conditions at the growth temperature.
ｕｓ、Ａｓ ２３を２μｍ程度９次にアンチ・メルトパ
ークｎ型Ｉ”０１６ Ｇａ［４Ａｓｕｉ ＰＱ４ｒｓ層
２４を０．５μｍ程ＪｆＬＰＥ成長した断面である。こ
のとき、ウェーハの周縁部２８ではＩ ｎ 、−ｓ Ｇ
ａ ｓ Ａ ｓ層２３のいわゆるエツジ・グロースと呼
ばれる異常成長が起っておりｅ Ｉ ｎ ｔ −ｓ
Ｇａ ” Ａ ｓ層の層厚をｉ、ｏμｍ以上にした時１
％に顕著であシ歇ｌＯμｍの高さに達することもある８
次にこの様なウェーハ上ＫＩｎＰを連＆１ｔＬＰＥ成長
した場合の結果の一例を第３図に示すが、ウェーハの中
央領域２０においてはｎ−ＩｎＰＪ−２５を成長した彼
も比較的良好な結晶性を有するのと比較して、ウェーハ
の端領域２８においては、いったん成長したＩｎ、−、
ＧａｇＡａ ２３及びｌ１ｍ１ｊＧａｎＡｓｙＰ、−、
２４層がＩｎＰ成長溶液中に溶けこんでなくなってしま
い′、その領域を基点にしてミスフィツト転位２９がＩ
ｎＰ層２層中５中量に発生する。また、この様なミスフ
ィツト転位はウェー／・の中心領域２０まで伸びている
ことがしばしばあり、良品質を得る成長方法が望まれて
いる。This is a cross section of a 9-order anti-melt park n-type I"016 Ga[4Asui PQ4rs layer 24 grown by JfLPE to a thickness of about 0.5 μm on a 9-order anti-melt park n-type I"016 Ga[4Asui PQ4rs layer 24 of about 2 μm. At this time, at the peripheral edge 28 of the wafer, I n , - s G
Abnormal growth, so-called edge growth, of the a s A s layer 23 is occurring, and e I n t -s
1 when the layer thickness of the Ga''A s layer is i,oμm or more
%, and can reach a height of 10 μm8.
Next, Fig. 3 shows an example of the results obtained when KInP is grown on a wafer by serial & 1tLPE.In the central region 20 of the wafer, he also grew n-InPJ-25 and found relatively good crystallinity. In the edge region 28 of the wafer, once grown In, -,
GagAa 23 and l1m1jGanAsyP, -,
The layer 24 dissolves into the InP growth solution and disappears, and misfit dislocations 29 start from that region.
It occurs in 5 out of 2 nP layers. Furthermore, such misfit dislocations often extend to the central region 20 of the way/., and a growth method that provides good quality is desired.
本発明の目的は上記したような特にＩｎ、−、Ｇａ。The object of the present invention is particularly to the above-mentioned In,-,Ga.
ＡｓあるいはＩ町−Ｇａ ｚ Ａ ｓｙ Ｐｒ−ｙ層の
比較的厚い膜を必要とする多層液相エピタキシャル成長
方法を工夫して欠陥が少なく均一性のよい高品質エピタ
キシャル成長層を形成するものである。The multilayer liquid phase epitaxial growth method, which requires a relatively thick film of As or I-GazA sy Pr-y layer, is devised to form a high-quality epitaxial growth layer with few defects and good uniformity.
本発明の液相エピタキシャル成長方法は、少くともＩｎ
Ｐ基板上Ｋ Ｉｎ、ｊＧａ、 Ａｓ ＴｏるいはＩｎ、
−。The liquid phase epitaxial growth method of the present invention comprises at least In
K In, jGa, As To or In on P substrate,
−.
Ｇａ１ＡｓｙＰｌ□（Ｊｌ≧０．２４．ｙ層０．５５）
液相エピタキシャル層を液相エピタキシャル成長後、液
相エピタキシャル成長層の周縁を除去した後で、前記液
相成長層上にＬｎＰ層を液相エピタキシャル成長するこ
とを特徴とする液相エピタキシャル成長方法である。Ga1AsyPl□ (Jl≧0.24.y layer 0.55)
This is a liquid phase epitaxial growth method characterized in that after a liquid phase epitaxial layer is grown by liquid phase epitaxial growth, a peripheral edge of the liquid phase epitaxial growth layer is removed, and then an LnP layer is grown by liquid phase epitaxial growth on the liquid phase growth layer.
次に本発明の優れた利点について一実施例に４とずいて
＃ｌ明する。本実施例でＦｉ Ｉｎ、−、Ｇａｍ Ａｇ
を光吸収層とする人ＰＤ及びＦＤ用ウェーハの結晶成長
例であり、第４図Ｋｓｓｏｔｒから６００°Ｃ糧度の飽
和溶液を用いて０．２°Ｃ／分糧度の冷却速度で成長を
行っ九ウェーハの概略断面図を示す。成長用＆−）は横
型スライド＆−）で成長用溶液を少くとも２．ケ有して
いる。成長方法は例えば６５００Ｃ飽和温度で１時間１
度保持後０．２°Ｃ／分で冷却を開始し、６４０°Ｃに
達したらすみやかＫｎ”−ＩｎＰ（１００）基板３１を
ＩｎＰバッファ一層成長用溶液下に位動することＫよ’
Ｉ） ｎ −ＩｎＰバッファ一層３２を成長する。次に
６３５°ＣＫ達したら６５０°ＣでＩｎ溶液にＧａ及び
Ａ３が一定飽和量仕込まれ九溶液下に前記１ｎＰ基板３
１を移行することによりｎ” ＩｎＰ バッファ一層
３２の成長を停止し、ひき続Ｉｎ型Ｉｎ、−，Ｇａ、
Ａｓ層３３を成長する。ここで４分程度成長することに
より２〜３μｍｌ！度の層厚のＩｎ、−、Ｇａ、 Ａｓ
層３３を得ることができる。所定時間Ｔｒｒ、−，Ｇａ
、 Ａｓ層３３をＬＰｇ成長後ＩｎＰ基板３１をＩｎ、
ｓＧａ、 Ａｓ成長用溶液下から移動し、成長炉の温度
を急冷して室温付近く達した後堰ヤ出したも・Ｏである
。ここでは成長用１１１液の大きさをＩｎＰ基板よシ小
さくし九場合の結果を図に示し九が、成長用溶液の大き
さをＩｎＰ基板より大きくしても状況は同じであＪ）
ＩｎＰ基板の中央領域３０においては％に３ｐｍ８度の
Ｉｎ、−、Ｇａ、 Ａｓ層３３が得られるのと較べて、
基板のＬＰＥ成長端３５でのＩｎ、−、Ｇａ、 Ａｓ層
３３は異常成長しており数１０μｍの高さに達する０次
に少くともとのウェーハのＬＰＩ成長端の異常成長領域
を切断除去（第４図中Ａ −Ａ’線で示した部分より切
断）した後、このＩｎ、−、Ｇａ、人３層３３を有する
ＩｎＰ基板３１を前記同様の横型スライドボートを有す
る成長炉中に設置し、昇温して６１５°Ｃ飽和温度で１
時間程度保持後、急冷を行ない６００°ＣＫたつしたな
らば降下温度を０．２６Ｃ／分に移行し、このときＩｎ
１．−Ｍ Ｏ８５Ａｓｙｐ、−、（ｍ ＝０．２４．
Ｙ＝０．５５ ）層を ９１Ｏ秒程度成長
することＫより０．６μｍ １１１１のｆｉｎ型Ｉｎ−
８Ｇｌ、 ＡｓｙＰｌ−、層３４を得る。ひきつづきａ
ｌｌＩｎＰ層３５を３〜５μｍｌｉ度所定時間により成
長した結果の概略断面図をｍ５図に示す。Next, the excellent advantages of the present invention will be explained by referring to one embodiment. In this example, Fi In, -, Gam Ag
This is an example of crystal growth of a PD and FD wafer with a light-absorbing layer, and the growth was carried out at a cooling rate of 0.2°C/min using a saturated solution at 600°C from Figure 4 Kssotr. A schematic cross-sectional view of a nine-way wafer is shown. For growth &-), use a horizontal slide &-) to apply the growth solution at least 2. I have. The growth method is, for example, 1 hour at 6500C saturation temperature.
After holding the temperature, start cooling at 0.2°C/min, and as soon as the temperature reaches 640°C, move the Kn''-InP (100) substrate 31 under the InP buffer layer growth solution.
I) Grow an n-InP buffer layer 32. Next, when 635°CK is reached, a certain saturation amount of Ga and A3 is charged into the In solution at 650°C, and the 1nP substrate 3 is placed under the solution.
1, the growth of the n'' InP buffer layer 32 is stopped by transferring the InP buffer layer 32, and the subsequent In-type In,-,Ga,
An As layer 33 is grown. By growing here for about 4 minutes, 2-3 μml! Layer thickness of In, -, Ga, As
A layer 33 can be obtained. Predetermined time Trr, -, Ga
, After growing the As layer 33 with LPg, the InP substrate 31 was grown with In,
The sGa and As were removed from under the growth solution, the temperature of the growth reactor was rapidly cooled, and after the temperature reached almost room temperature, the molten metal was poured out. Here, the results are shown in the figure when the size of the growth solution is made smaller than that of the InP substrate.However, the situation is the same even if the size of the growth solution is made larger than that of the InP substrate.
Compared to the central region 30 of the InP substrate, an In, -, Ga, As layer 33 with a thickness of 3 pm and 8 degrees is obtained.
The In, -, Ga, As layer 33 at the LPE growth edge 35 of the substrate has grown abnormally and reaches a height of several tens of micrometers. After cutting from the part shown by line A-A' in FIG. , the temperature was increased to 615°C at the saturation temperature of 1
After holding the temperature for about an hour, quenching is performed and when the temperature reaches 600°CK, the temperature drop is shifted to 0.26C/min.
1. -M O85Asyp, -, (m = 0.24.
Y=0.55) layer was grown for about 910 seconds to form a fin-type In-
8Gl, AsyPl-, layer 34 is obtained. Continued a
A schematic cross-sectional view of the result of growing the llInP layer 35 to a thickness of 3 to 5 μm for a predetermined time is shown in figure m5.
本実施例においてはＩ ｎ、−、Ｇａ、Ａ６層の異常成
長領域、りまりウェーハのＬＰＢ成長端を除去すること
Ｋより第２図及び第３図を用いて説明し丸場合と較べて
、上記Ｉｎ、−、Ｇａ＋、ム＄上Ｋ ■町−ｓ Ｇａｇ
ＡａｙＰ、□ｙ層を介してであるがＩｎＰ層を成長し
たときウェーハ周縁でもへテロ層構造を構成でき、 Ｉ
ｎＰ層中にすべ夛転位であるところのンスフィット転位
の導入が極端に抑制されており高品質なＡＰＤ用結晶が
得られる。１＃、実施例ではＩｎＰ−Ｉｎ山直５−Ｉｎ
ＧａＡｓＰ−ＩｎＰ層構造とし九が＊ ＩｎＰ−ＩｎＧ
ａＡｓ −ＩｎＰ、 ＩｎＰ ＩｎＧａＡｓＰ−ｌ５Ｐ
層構造としてもよい。In this example, the removal of the abnormal growth region of the In, -, Ga, and A6 layers and the LPB growth edge of the Marimari wafer will be explained using FIGS. 2 and 3, and will be compared with the round case. Above In, -, Ga+, Mu $ upper K ■ Town -s Gag
When an InP layer is grown through the AayP, □y layer, a heterolayer structure can be formed even at the wafer periphery, and I
The introduction of sfit dislocations, which are planar dislocations, into the nP layer is extremely suppressed, and a high-quality crystal for APD can be obtained. 1#, InP-In Yamanao 5-In in the example
GaAsP-InP layer structure and nine * InP-InG
aAs-InP, InP InGaAsP-15P
It may also have a layered structure.
以上説明し友様に１本発明の要点紘厚膜液相エピタキシ
ャル成長層が必要な場合にウェーハ周縁の異常成長領域
を除去するという簡単な工夫であるがＩｎ、、 Ｇａｊ
ＡｓｙＰｌ−、０液相エピタキシヤル成長の場合には特
に１μｍ以上の膜厚を必要とする場合には１≧０．２４
． 、≧０．５５組成以上のＩｎ、−、Ｇａ。Having explained the above, I would like to share with you one of the main points of the present invention.It is a simple device to remove the abnormally grown region at the periphery of the wafer when a thick film liquid phase epitaxially grown layer is required.
AsyPl-, 0 In the case of liquid phase epitaxial growth, especially when a film thickness of 1 μm or more is required, 1≧0.24.
．． , ≧0.55 or more of In, -, Ga.
Ａｓ、 Ｐ、、の場合ｋｌ？ｉＫウェーハ端でのＬＰＥ
成長層に異常成長が大きいことが経験的に知られてお）
光源としてのＬＥＤ等の比較的厚膜を必要とする場合の
液相エピタキシャル成長においても効果を有しており、
良品質な厚膜を有する多層構造液相エピタキシャル成長
が可能となる。As, P, , kl? LPE at iK wafer edge
It is known empirically that abnormal growth is large in the growth layer)
It is also effective in liquid phase epitaxial growth in cases where relatively thick films are required, such as in LEDs used as light sources.
It becomes possible to liquid-phase epitaxial growth of a multilayer structure with a high-quality thick film.
菖１図はＩ ｎ 、−ｘ Ｇａ ｚ Ａ ｓｙ Ｐｌ−
ｙを用いたＡＰＤの報告例であシ、１１はｎ ＩｎＰ
基板、１２はｎ＋−ＩｎＰバッファ一層、１３＃′ｉｎ
型Ｉｎ、−、Ｇａ、 Ａｓ。
Ｐ 層、１４はｎ型ＩｎＰ層であり、１５はＰ型子１′
″ｙ
鈍物を選択拡散技術によシ前記１４層中に形成し友もの
である。第２図はＩｎ、、 Ｇａｓ Ａｓ層の比較的厚
膜液相エピタキシャル成長した場合の成長端での異常成
長を示し友ものであり、２１はｎ ＩｎＰ基板、２２
はｎ” ＩｎＰバッファ一層、２３はａｌｌＩ ｎ ｓ
、−５Ｇａ ｊＡｓ層、２４はｎ型Ｉｎ、−ｓ Ｇａ
ｓ Ａｓ、 Ｐｒ−。
層である。第３図は第２図のウェーノ・Ｋ ｎ型−Ｉｎ
Ｐ層２層管５相成長した場合のウェーノ・断面を示して
おり、ウェーハ周縁、％に上記第２図のＩｎ Ｇａ、
Ａｓ異常成長領域上Ｋ Ｉ ｎ、−、Ｇａ、ＡａｙＰ
、−ｙ層２４を介してＩｎＰ層２層管５長したとき１町
−Ｇａ、Ａｓ及びＩ ｎ Ｉ−＃Ｇａ ｇ Ａ ａｙ
Ｐｌ−ｙ層がとけ、この傾斌を起点にしてミスフィツト
転位がｎ−１ｎＰ層２５中に伸びていることを示してい
る。第４図、第５図は本発明の一！Ｉ！施例を示し丸も
のであシ、第４図の３１はｎ−ＩｎＰ層、３２はｎ”−
ＩｎＰバッファ＋
一層、３３はｎｌｌＩｎＰ層である。この様なウェーハ
のＩｎ、−ｊＩＧａ、 Ａｓ成長端の異常成長領域を除
去する。＠５図は、第４１１に示し丸様な）１．−、Ｇ
ａ、ムＳ威長異常端除去ウェーハを用い液相エピタキシ
ャル成長したものであシ３４はｒｓ Ｉ！ Ｉｎ、−、
Ｇａ、 ＡｓＰ、−ｙ層、３５はｎｌｌＩｎＰ層である
。
第１図
５
蔦２図
第３図
第４図
第５図
１４１−Iris 1 diagram is I n, -x Gaz A sy Pl-
This is a reported example of APD using y, 11 is n InP
Substrate, 12 is n+-InP buffer single layer, 13#'in
Type In, -, Ga, As. P layer, 14 is n-type InP layer, 15 is P-type layer 1'
A blunt material is formed in the 14 layers by selective diffusion technique. Figure 2 shows the abnormal growth at the growth edge when relatively thick liquid phase epitaxial growth of an In, Gas, and As layer is performed. 21 is an n InP substrate, 22
is n” InP buffer single layer, 23 is all I n s
, -5Ga jAs layer, 24 is n-type In, -sGa
s As, Pr-. It is a layer. Figure 3 shows the Weno-K n-type shown in Figure 2.
The figure shows a wafer cross-section when five-phase P-layer two-layer tube is grown.
K I n, -, Ga, AayP on As abnormal growth region
, - When the length of the InP two-layer tube is 5 through the y layer 24, one town - Ga, As and I n I - # Ga g A ay
This shows that the Pl-y layer melts and misfit dislocations extend into the n-1nP layer 25 starting from this tilt. Figures 4 and 5 are part of the invention! I! The embodiment is shown in a round shape, 31 in FIG. 4 is an n-InP layer, and 32 is an n''-
InP buffer + layer, 33 is nlllInP layer. Abnormal growth regions at the In, -jIGa, and As growth ends of such a wafer are removed. @5 Figure 411 shows a round shape) 1. -,G
a, Liquid phase epitaxial growth using a wafer with anomalous edges removed. 34 is rs I! In, -,
Ga, AsP, -y layer, 35 is nllInP layer. Figure 1 5 Ivy Figure 2 Figure 3 Figure 4 Figure 5 141-
Claims (1)
い紘Ｉ ｎ ＋ −ＨＧ ａ ｘ人１．Ｐ、−、（０，
４７＞廖≧０．２４．１＞ｙ≧０．５５ ）層を液相エ
ピタキシャル成長し先後、当該液相エピタキシャル成長
層が形成されているクエハーの周縁を除去し１次いでＩ
ｎＰ層を前記液相エピタキシャル成長層上に液相エピタ
キシャル成長することを特徴とする液相エピタキシャル
成長方法。At least on an InP substrate K In, -, Gap < As6 - HG a x person 1. P,−,(0,
47>Liao≧0.24.1>y≧0.55) layer is grown by liquid phase epitaxial growth, and then the periphery of the wafer on which the liquid phase epitaxial growth layer is formed is removed and then I
A liquid phase epitaxial growth method, characterized in that an nP layer is liquid phase epitaxially grown on the liquid phase epitaxial growth layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56206563A JPS58107628A (en) | 1981-12-21 | 1981-12-21 | Loquid phase epitaxial growth method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56206563A JPS58107628A (en) | 1981-12-21 | 1981-12-21 | Loquid phase epitaxial growth method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58107628A true JPS58107628A (en) | 1983-06-27 |
Family
ID=16525460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56206563A Pending JPS58107628A (en) | 1981-12-21 | 1981-12-21 | Loquid phase epitaxial growth method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58107628A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033322A (en) * | 1989-05-31 | 1991-01-09 | Shin Etsu Handotai Co Ltd | Liquid phase epitaxy method |
| JPH0371619A (en) * | 1989-08-11 | 1991-03-27 | Sanyo Electric Co Ltd | Method of formation of semiconductor thin film |
| JPH0373519A (en) * | 1989-08-14 | 1991-03-28 | Hoxan Corp | Formation of polycrystalline silicon film on semiconductor substrate |
| JPH0373518A (en) * | 1989-08-14 | 1991-03-28 | Hoxan Corp | Formation of polycrystalline silicon film on wafer |
-
1981
- 1981-12-21 JP JP56206563A patent/JPS58107628A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033322A (en) * | 1989-05-31 | 1991-01-09 | Shin Etsu Handotai Co Ltd | Liquid phase epitaxy method |
| JPH0371619A (en) * | 1989-08-11 | 1991-03-27 | Sanyo Electric Co Ltd | Method of formation of semiconductor thin film |
| JPH0373519A (en) * | 1989-08-14 | 1991-03-28 | Hoxan Corp | Formation of polycrystalline silicon film on semiconductor substrate |
| JPH0373518A (en) * | 1989-08-14 | 1991-03-28 | Hoxan Corp | Formation of polycrystalline silicon film on wafer |
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