JPS5810756B2 - image display device - Google Patents

Description

[Detailed description of the invention] The present invention relates to an image display device.

Conventionally, when displaying monochromatic two-level brightness (single color and black and white), the memory used for color display was not used.
Memory usage efficiency is very poor.

This was a contributing factor to the rise in equipment prices.

The present invention has been made in consideration of these points.

For example, when displaying text, etc., it is displayed in detail with a single color and two levels of brightness (for example, black and white), and when displaying a single figure, etc., it is displayed coarsely but colorfully, or attractively with shading, and memory is used effectively. The present invention provides an image display device that has the following features.

Furthermore, it is an object of the present invention to provide an image display device that can easily display the movement of an image, or can freely change the color of each memory pattern to provide an attractive display.

An embodiment of the present invention will be described below based on the drawings.

Now single color 2 level brightness high density display in A mode. Set the color rough density display to B mode.

In FIG. 1, Ml, M2. M3. M4 is an image memo IJ that stores a pattern such as one character, one figure, etc., CH is a horizontal clock input terminal, and Cv is a vertical clock input terminal.

El and El are operation enable input terminals, RH is a horizontal address register reset input terminal, RV is a horizontal address register input terminal, and 0 is an output terminal that outputs the memory contents specified by the horizontal and vertical address registers.

The memos IJ M 1 to M4 are horizontal. If the vertical clock signal causes the address register to be incremented by 1,
It is assumed that unless both of the operation permission input terminals E1 and El are active, no addition will occur and no output will appear at the output terminal 0.

21 is a clock control circuit, and each memory M1 to M4 (7)
The horizontal clock signal, vertical clock signal, and operation permission signal to be sent to terminals CH2Cv and El,
Switch by B.

31 is a clock generation circuit that outputs lock signals, permission signals, and reset signals necessary for memory reading to terminal CVA.
, CVB, CHA, CHB and E I H,, E I L
.

EIB E2L E2RE2B and RV.

RH+ also generates horizontal synchronization signals and vertical synchronization signals necessary for the rask scan display device 51 at terminals H and V.

Next, the rask scan display device 51 uses the clock generation circuit 3.
1 driven by the horizontal and vertical synchronization signals from 1;
R (red) and G (green) from color output control circuit 41
, (blue) signal is used for display.

Further, the color output control circuit 41 is connected to each memory IJM1.
~M4 output R, G.

Either one of the B signals or a combination of a plurality of colors is sent to the RuskScan display device 51 as an output.

FIG. 2 is a time chart showing the output of the clock generation circuit 31 shown in FIG.
) IA It has twice the period of CVA.

In mode A, the signals sent to each memory IJM1 to M4t are controlled by the clock control circuit 21 as follows.

CV=CVA CH=CHA E1 of Ml and Ml=EIH E1 of M3 and M4=EIH E2 of Ml and M3=E2L E2 of Ml and M4=E2R Therefore, referring to FIG. 2, the display screen P at this time corresponds to each memo IJ M 1 to M4 + 4 as shown in Figure 3.
It is divided into two categories.

The pattern output of each memory M1 to M4 can be outputted in a desired color by the color output control circuit 41.

That is, if it is white, the output of each memory outputs all RGB signals to the rask scan display device 51.

In mode B, the signals sent to each memory IJM1 to M4 are controlled by the clock control circuit 21 as follows.

CV=CVB CH=CHB El (for each memory) = EIB E2 (for each memory) - E2B Therefore, refer to FIG. They are overlapping like this.

Here, each of the memos IJM1 to IJM4 is read out at half the speed both horizontally and vertically compared to the case of mode A.

Then, the color output control circuit 41 controls to output the output of the memory M1 to R, the output of the memory IJM2 to G, the output of the memory M3 to B, and not output the output of the memory IJM4 to R2O and B. Then R2 on one screen
The eight-color (including black) screen displayed by O and B is displayed at 1/4 the density of mode A.

In the above explanation, the output of memo IJM4 was ignored, but for example, if another pattern of R is written, memo IJMI and M4
The color output control circuit 41 may switch the display to the vertical blanking period (FIG. 2) to display the memory IJM4, and this operation may be performed by switching alternately between M1 and M4.

In this case, the R image on the display screen is not displayed at a relatively low speed, even though the memo January pattern is written.
Dynamic E allows you to display moving patterns without flickering.

In addition, the pre-color output control circuit 41 can perform highly entertaining displays such as switching the colors of each pattern at high speed.

Although the color display Q has been explained in detail in this embodiment, the same can be done by using a plurality of memories and using the RGB output of the two-color output control circuit as a signal representing brightness (
From this, gray scale display can also be easily implemented.

Furthermore, the number of screens is not limited to four, and it is also possible to perform color display and clay scale display at the same time.

As described above, the present invention [therefore, it is possible to display on the same monitor, such as a television, a screen that requires detailed depiction such as a single character, and a screen that is better to display color distinctions (i.e., graphics) even if it is relatively rough. It can be expected to have high memory usage efficiency and low cost.

It is also possible to display dynamic images.

It is possible to obtain an attractive display that is rich in entertainment value.

[BRIEF DESCRIPTION OF THE DRAWINGS] The drawings show one embodiment of the present invention, and FIG. 1 is a block diagram thereof, FIG. 2 is a time chart showing the output of a clock generation circuit, and FIG. 3 is a monochrome two-step brightness high-density display. FIG. 4 is an explanatory diagram showing the correspondence between the display screen and memory in the case of color coarse density display. M1 to M4... Image memory, 21...
Clock control circuit, 31... Clock generation circuit, 41... Color output coat roll circuit, 51...
...Raster scan display device.

Claims (1)

[Claims] 1. A clock control circuit that switches and controls fine and coarse clock signals supplied to each memory from a plurality of image memories capable of controlling memory read addresses and a clock generation circuit between a brightness display mode and a color display or grayscale display mode; a color output control circuit that outputs each memory output as one of RGB or a combination of a plurality of colors;
Driven at the same horizontal and vertical frequency in each mode, the output of the color output control circuit is used to display a monochromatic two-step brightness high-density display for each memory output, and a coarse-density color display or grayscale display in which each memory output is superimposed. 1. An image display device comprising: a raster scan display device that switches between and displays images.