JPS61107288A - Image memory system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention enables brightness gradation and color display without loss of resolution by combining a high-resolution image memory and a low-resolution image memory. The present invention relates to an image memory system configured as described above.

<Prior art> Conventionally, in high-resolution image memory systems capable of displaying brightness gradation and color, high-resolution memory is used to express gradation K.
, had to be used. Therefore, in order to increase the number of gradations and colors, it is necessary to add a huge amount of memory capacity, which may cause economical and spatial problems. For example, the resolution of the 1024×1024 image shown in Figure 2 is 25
To express 6 (2s) gradations, the image memory needs to be 8M.
Means for solving the problem of requiring a large bit capacity〉 The present invention combines a high-resolution image memory and a low-resolution image memory, and the one-resolution image memory has a shape of the object to be displayed. The main image data such as ``Brightness gradation and color'' are stored in the low-resolution memory, and the attribute image data such as the brightness gradation and color of the object is stored. , which is configured so that it can be displayed in color.

<Example> FIG. 1 is a block diagram of the present invention, and a 1024×10
This is an example in which the resolution level is 24 and the gradation is 256 (28), and FIGS. 5 and 4 are examples of displayed images.

In FIG. 1, timing control 4-21 includes X address AI, 7 address Ay, and 7 address Ay for image memory access.
and a period generating circuit generates a timing signal T. X address AXI7 address Ay are respectively K O-X 9
+7Ck-71, and XO'=X9e7o~y at the addresses of two sets of image memories 2a and 21) for high resolution.

are given 10 bits each. The six sets of low-resolution image memories 5, to 5f are given 9 bits of the X17 address (XI ``''''XI + 71' = 79).

Accordingly, main image data of 1024 x 1024 pixels is input to the high resolution image memories 2a to 21:1, and attribute image data of 512 x 512 pixels to the low resolution image memories 3a to 3fK. The timing controller 1 is
High resolution memory 2a.

After generating the x7 address of 2b from 0 to 1023, the y address is incremented by 1 and the y address counts to 1024, thereby generating an address of 1024Xi024. Similarly, XO+7 is applied to low resolution image memories 3a to 3f.
9 bits excluding 0 are output to generate a 512x512 address.

With the above configuration, the high-resolution image can express four colors or four brightness gradations (22). On the other hand, low-resolution images can be expressed in (26) 64 colors or 64 brightness levels. The main image data DM stored in the high-resolution image memories 2a and 2b is stored in the color or brightness gradation generation circuit 4.
Attribute image data DA that is given to the main color or luminance signal and stored in the low resolution image memories 3a to 5f
,,.

is converted into an attribute color or brightness signal by a color or brightness gradation generation circuit 5, and the two signals are converted into an attribute color or brightness signal by a combination circuit 6.
It is possible to express 256 (2') colors or 256 (28) gradations. The synchronization generation circuit 7 is
Timing core) o -21 generates the horizontal synchronization signal after generating the 1024 X address, and generates the 1024 Y address.
After generating the address, a vertical synchronization signal is generated. FIG. 3 shows a specific example of the nine strokes displayed by this embodiment, and FIG. 4 is an enlarged view of a part 100 thereof.

In this example, a green triangle G, a red circle R, and a white cross mark 1 are displayed, but the intersection of green G and red R is '#B, and the intersection of self-blame and green a is yellow Y. The color generating circuit 4.5 and the combining circuit 6 are adjusted so that Also, the background color of the part containing the figure is purple P, and the background color is black. In this case, only 7 colors are expressed, but Sakadai 2
Needless to say, up to 56 colors can be expressed. According to FIG. 4, the image quality synthesized by the display area 20 of the high-resolution image memory and the display area 30 of the low-resolution image memory is expressed as a resolution trap of the high-resolution image memory. It's obvious. In addition, in the embodiment, two high-resolution image memories and six low-resolution image memories were used, but image memories that match the characteristics of the displayed image such as resolution, brightness gradation, color, etc. By adopting this configuration, it is possible to make effective use of the space economically and spatially.

Furthermore, it can be directly applied to applications such as general television images where only the black and white gradation display requires high resolution and only the color portion requires low resolution.

<Effects of the Invention> As explained above, in the present invention, by using high-resolution and low-resolution image memories, the memory capacity that conventionally required 8 Mbits can be improved without reducing the resolution of image shapes. On the other hand, it has the effect of being able to display colors and gradations with a small memory capacity of A5M bits. Furthermore, even when displaying images or figures with relatively high redundancy, the memory capacity can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image memory system of the present invention;
Figure 2 is an explanatory diagram showing the configuration of a conventional image memory;
The figure is an explanatory diagram showing an example of an image displayed by the image memory system of the present invention, and FIG. 4 is an enlarged view of FIG. 5. 2a, 2b...High resolution image memory 5a-5f...Low resolution image memory 4.5...
Color, brightness gradation generation circuit 6...Composition circuit 7...Period generation circuit and above

Claims (1)

[Claims] In the image memory of the raster scan volume display device,
The image memory for storing image data is provided with an image memory consisting of a main image data memory and an attribute image data memory having different memory capacities, and the main image memory stores image data of the entire image such as the shape. An image memory system characterized in that an attribute image memory stores brightness gradation or color image data, and when an image is reproduced, an image is displayed by combining the image data of the image memory.