JPS58104065U

JPS58104065U - Time base correction device for multi-channel magnetic recording/reproducing device

Info

Publication number: JPS58104065U
Application number: JP19417481U
Authority: JP
Inventors: 加藤　哲郎
Original assignee: ソニー株式会社
Priority date: 1981-12-31
Filing date: 1981-12-31
Publication date: 1983-07-15

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案に係る時間軸補正装置の一実施例を示す
ブロック図である。第２図は上記実施例における書込み
クロック発生回路の具体的な構成例を示す回路図である
。第３図は上記書込みクロック発生回路の動作を示すタ
イムチチャートである。第４図は上記実施例における時
間軸補正用のデジタルメモ□すの原理品な構成を示す一
式図である。１、　２．　３・・・磁気ヘッド、１０・・・磁気テー
プ、４１．４２，４３・・・Ａ／Ｄ変換器、５１．５２
゜５３・・・デジタルメモリ、５５，５６，５７．５８
・・・ＩＨメモリ、６１，６２．６３・・・Ｄ／Ａ変換
器、？１．　７２．　７３・・・同期分離回路、９１，
９２゜９３・・・同期化回路、１００・・・書込みクロ
ック発生回路、１１０・・・書込みアドレスカウンタ、
１２０・・・読出しアドレスカウンタ。FIG. 1 is a block diagram showing an embodiment of a time axis correction device according to the present invention. FIG. 2 is a circuit diagram showing a specific example of the configuration of the write clock generation circuit in the above embodiment. FIG. 3 is a timing chart showing the operation of the write clock generating circuit. FIG. 4 is a complete diagram showing the basic configuration of the digital memo for time axis correction in the above embodiment. 1, 2. 3... Magnetic head, 10... Magnetic tape, 41.42, 43... A/D converter, 51.52
゜53...Digital memory, 55, 56, 57.58
...IH memory, 61,62.63...D/A converter, ? 1. 72. 73... synchronous separation circuit, 91,
92°93...Synchronization circuit, 100...Write clock generation circuit, 110...Write address counter,
120...Read address counter.

Claims

[Scope of utility model registration request]

A digital memory for time axis correction is installed in each signal line of the reproduction system in a multi-channel magnetic recording/reproduction device that divides a color video signal into each color signal side and performs multi-channel recording/reproduction. In a device that performs time axis correction by writing the data into each digital memory and reading it out using a regular readout clock, the synchronization signal generated at the earliest timing among the synchronization signals included in the playback signal of each channel is A write address counter that counts as a count pulse to form a write address signal, and a synchronization circuit that synchronizes the write address signal from the write address counter with a synchronization signal of each channel, and is synchronized with the synchronization signal of each channel. A time axis correction device for a multi-channel magnetic recording/reproducing device, characterized in that an address for each digital memory write is specified by a write address signal.