JPH0181732U - - Google Patents
Info
- Publication number
- JPH0181732U JPH0181732U JP1987177157U JP17715787U JPH0181732U JP H0181732 U JPH0181732 U JP H0181732U JP 1987177157 U JP1987177157 U JP 1987177157U JP 17715787 U JP17715787 U JP 17715787U JP H0181732 U JPH0181732 U JP H0181732U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- delay time
- delay
- control
- decoding means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Description
第１図は本考案に係るビデオテープレコーダの
デジタルデイレイ回路のブロツク図、第２図はク
ロツク同期部においてカウンタ同期デイレイ原信
号Ｓ３が形成される様子を示すタイムチヤート、
第３図はデイレイタイム設定部１０における信号
のタイムチヤート、第４図はビデオテープレコー
ダのテープ走行系を示す平面図、第５図は磁気テ
ープの記録フオーマツトを示す拡大図である。
１０……デイレイタイム設定部、２１……受光
部、２２……シリアル・パラレル変換部、２３…
…データ変換部、３１……入力バツフア部、３２
……クロツク同期部、４１……マスタークロツク
発生部、４２……リフアレンス信号発生部、４３
……カウンタ用クロツク発生部。
FIG. 1 is a block diagram of a digital delay circuit of a video tape recorder according to the present invention, and FIG. 2 is a time chart showing how the counter synchronized delay original signal S3 is formed in the clock synchronization section.
FIG. 3 is a time chart of signals in the delay time setting section 10, FIG. 4 is a plan view showing the tape running system of the video tape recorder, and FIG. 5 is an enlarged view showing the recording format of the magnetic tape. 10...Delay time setting section, 21...Light receiving section, 22...Serial/parallel conversion section, 23...
...Data conversion section, 31...Input buffer section, 32
... Clock synchronization section, 41 ... Master clock generation section, 42 ... Reference signal generation section, 43
...Counter clock generator.
Claims (1)
信号を再生するコントロールヘツドと、リモコン
から送り出される遅延時間の情報を含んだデジタ
ル信号からなる遅延信号を解読する信号解読手段
と、その信号解読手段によつて検知された遅延時
間分だけ前記コントロール信号を遅延させて出力
するデイレイタイム設定部が設けられていること
を特徴とするビデオテープレコーダのデジタルデ
イレイ回路。 A control head that reproduces a control signal that controls the running state of the magnetic tape, a signal decoding means that decodes a delay signal consisting of a digital signal containing delay time information sent from a remote control, and detection by the signal decoding means. 1. A digital delay circuit for a video tape recorder, further comprising a delay time setting section that delays and outputs the control signal by a specified delay time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987177157U JPH0181732U (en) | 1987-11-19 | 1987-11-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987177157U JPH0181732U (en) | 1987-11-19 | 1987-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0181732U true JPH0181732U (en) | 1989-05-31 |
Family
ID=31468833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987177157U Pending JPH0181732U (en) | 1987-11-19 | 1987-11-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0181732U (en) |
-
1987
- 1987-11-19 JP JP1987177157U patent/JPH0181732U/ja active Pending
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