JPS5810369Y2 - multilayer wiring board - Google Patents
multilayer wiring boardInfo
- Publication number
- JPS5810369Y2 JPS5810369Y2 JP1977115025U JP11502577U JPS5810369Y2 JP S5810369 Y2 JPS5810369 Y2 JP S5810369Y2 JP 1977115025 U JP1977115025 U JP 1977115025U JP 11502577 U JP11502577 U JP 11502577U JP S5810369 Y2 JPS5810369 Y2 JP S5810369Y2
- Authority
- JP
- Japan
- Prior art keywords
- multilayer wiring
- wiring board
- power supply
- chip
- supply pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【考案の詳細な説明】
本考案は電子計算機等の電子機器に用いられ、複数個の
ＩＣチップを搭載する多層配線基板に関する。[Detailed Description of the Invention] The present invention relates to a multilayer wiring board that is used in electronic devices such as computers and has a plurality of IC chips mounted thereon.
従来の多層配線基板の１例を第１図、第２図に示す。An example of a conventional multilayer wiring board is shown in FIGS. 1 and 2.
第１図は従来の多層配線基板の平面図であり、参照数字
１は絶縁性基板、参照数字１３は多層配線基板の入出力
端子、参照数字９はＩＣチップのリード接続部、参照数
字１０はＩＣチップ搭載部、参照数字１４は接地電源供
給用パターンである。FIG. 1 is a plan view of a conventional multilayer wiring board, in which reference numeral 1 is an insulating board, reference numeral 13 is an input/output terminal of the multilayer wiring board, reference numeral 9 is a lead connection part of an IC chip, and reference numeral 10 is an input/output terminal of the multilayer wiring board. Reference numeral 14 in the IC chip mounting area is a ground power supply pattern.
この接地電源供給パターンの太さは従来の多層配線基板
では、はぼ均一であった。The thickness of this ground power supply pattern was almost uniform in conventional multilayer wiring boards.
第２図は従来の多層配線基板の部分的な断面図の１例で
あり、正又は負の電源供給用パターン１４は参照数字６
の第３導体層に形成されているが、接地電源供給用パタ
ーンと同様太さはほぼ均一である。FIG. 2 is an example of a partial cross-sectional view of a conventional multilayer wiring board, and the positive or negative power supply pattern 14 is indicated by reference numeral 6.
Although it is formed on the third conductor layer of the third conductor layer, the thickness is almost uniform like the ground power supply pattern.
このように、はぼ均一の太さの接地電源および正又は負
の電源供給用パターンを持った多層配線基板では、多層
配線基板の入出力端子付近に搭載されたＩＣチップまで
の直流電圧降下は小さいが、多層配線基板の中央付近に
搭載されたＩＣチップまでの直流電圧降下は非常に大き
くなってしまうという欠点があった。In this way, in a multilayer wiring board with a ground power supply and a positive or negative power supply pattern of approximately uniform thickness, the DC voltage drop to the IC chip mounted near the input/output terminals of the multilayer wiring board is Although it is small, it has the disadvantage that the DC voltage drop to the IC chip mounted near the center of the multilayer wiring board becomes extremely large.
本考案の目的は入出力端子からＩＣチップまでの接地お
よび正又は負の電源の直流電圧降下が大きい個所の直流
電圧降下を低減した多層配線基板を提供することにある
。An object of the present invention is to provide a multilayer wiring board that reduces the DC voltage drop at locations where the DC voltage drop is large in the ground and positive or negative power supplies from the input/output terminal to the IC chip.
本考案は、２以上のＩＣチップと、中央に近い部分を太
く端に近い部分を細くし前記ＩＣチップに電源を供給す
る電源供給用パターンとを含むことを特徴とする多層配
線基板を構成する。The present invention constitutes a multilayer wiring board characterized by including two or more IC chips and a power supply pattern that is thick near the center and thin near the edges and supplies power to the IC chips. .
次に本考案の一実施例について図面を参照して説明する
。Next, an embodiment of the present invention will be described with reference to the drawings.
本考案の一実施例の平面図を示す第３図では、本実施例
における多層配線基板の表面層は、入出力端子１３、Ｉ
Ｃチップのリード接続部９、ＩＣチップ搭載部１０、お
よび接地電源供給用パターン１４を含む。In FIG. 3 showing a plan view of an embodiment of the present invention, the surface layer of the multilayer wiring board in this embodiment includes input/output terminals 13, I
It includes a C chip lead connection part 9, an IC chip mounting part 10, and a ground power supply pattern 14.
また本実施例を示した第３図の部分的な断面図を示す第
４図は、絶縁性基板１．第１導体層２、第１絶縁体層３
、第２導体層４、第２絶縁体層５、第３導体層６を含む
。Further, FIG. 4, which shows a partial cross-sectional view of FIG. 3, which shows this embodiment, shows the insulating substrate 1. First conductor layer 2, first insulator layer 3
, a second conductor layer 4, a second insulator layer 5, and a third conductor layer 6.
ここで第３導体層６は、ＩＣチップのリード接続部９、
ＩＣチップ搭載部１０、および接地電源供給用パターン
１４より戒る。Here, the third conductor layer 6 includes the lead connection portion 9 of the IC chip,
The IC chip mounting portion 10 and the ground power supply pattern 14 are protected from each other.
また、参照数字２，４の導体層は信号用パターンおよび
正又は負の電源供給用パターンより戊る。Further, the conductor layers with reference numerals 2 and 4 are separated from the signal pattern and the positive or negative power supply pattern.
正又は負の電源供給用パターン４は第３図における接地
電源供給用パターン１４と同様に端に近い部分は細く、
中央に近い部分は太くなっている。The positive or negative power supply pattern 4 has a thin portion near the end, similar to the ground power supply pattern 14 in FIG.
The part near the center is thicker.
次に本実施例の効果について説明する。Next, the effects of this embodiment will be explained.
従来の多層配線基板では、第１図において中央付近に消
費電力の最も大きいＩＣチップが搭載された場合、多層
配線基板の入出力端子から多層配線基板の中央付近に搭
載されたＩＣチップまでの接地電源および正又は負の電
源の直流電圧降下は非常に大きくなるが、本実施例にお
いては、中央付近の接地電源および正又は負の電源供給
用パターンは太くなっているので、中央付近に搭載され
たＩＣチップまでの直流電圧降下は、従来の多層配線基
板と比較してかなり小さくなるという利点がある。In a conventional multilayer wiring board, if the IC chip with the largest power consumption is mounted near the center in Figure 1, the grounding from the input/output terminal of the multilayer wiring board to the IC chip mounted near the center of the multilayer wiring board The DC voltage drop of the power supply and the positive or negative power supply becomes very large, but in this example, the ground power supply and the positive or negative power supply pattern near the center are thick, so they cannot be mounted near the center. This has the advantage that the DC voltage drop to the IC chip is considerably smaller than that of conventional multilayer wiring boards.
また、パターンの幅を任意に細くすることにより多層配
線基板の端に搭載されたＩＣチップまでの直流電圧降下
は、従来の多層配線基板と比較して大きくなり、同一の
多層配線基板内のＩＣチップ間の接地電源および其の電
源電位のバラツキが小さくなるという利点がある。In addition, by arbitrarily narrowing the width of the pattern, the DC voltage drop to the IC chip mounted on the edge of the multilayer wiring board becomes larger than that of a conventional multilayer wiring board. This has the advantage that variations in the ground power supply and its power supply potential between chips are reduced.
なお、本実施例では基板の中央部分を経由して通る供給
用パターンは、両端においても同じ太さで太くしたが、
本考案は必ずしもこれに限定されず中央部分のみを太く
シ、端部を細くしてもよい。In addition, in this example, the supply pattern passing through the center part of the board was made thick with the same thickness at both ends.
The present invention is not necessarily limited to this, but only the central portion may be thicker and the ends may be thinner.
本考案は以上説明したように、多層配線基板において、
接地電源および正又は負の電源供給用パターンの幅を中
央に近い部分は太く、端に近い部分は細くなるよう適当
に変化させることにより、接地電源および正又は負の電
源の直流電圧降下の大きい部分の直流電圧降下を低減で
きる効果がある。As explained above, the present invention, in a multilayer wiring board,
By appropriately changing the width of the grounding power supply and positive or negative power supply pattern so that the part near the center is thick and the part near the edge is thinner, the DC voltage drop of the grounding power supply and positive or negative power supply is large. This has the effect of reducing the DC voltage drop in the parts.
第１図は複数個のＩＣチップを搭載した従来の多層配線
基板の平面図、第２図は第１図の部分的な断面図である
。
第３図は本考案の一実施例を示す多層配線基板の平面図
、第４図は第３図の部分的な断面図である。
１・・・・・・絶縁性基板、２・・・・・・第１導体層
（信号用パターン）、３・・・・・・第１絶縁体層、４
・・・・・・第２導体層（正又は負の電源供給パターン
）、５・・・・・・第２絶縁体層、６・・・・−・・第
３導体層、７・・・・・・第３絶縁体層、８・・・・・
・第４導体層、９・・・・・・ＩＣチップのリード接続
部、１０・・・・・・ＩＣチップの載部、１１・・・・
・・ＩＣチップのリード、１２・・・・・・ＩＣチップ
、１３・・・・・・入出力端子、１４・・・・・・接地
電源供給用パターン。FIG. 1 is a plan view of a conventional multilayer wiring board on which a plurality of IC chips are mounted, and FIG. 2 is a partial sectional view of FIG. 1. FIG. 3 is a plan view of a multilayer wiring board showing an embodiment of the present invention, and FIG. 4 is a partial sectional view of FIG. 3. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... First conductor layer (signal pattern), 3... First insulating layer, 4
...Second conductor layer (positive or negative power supply pattern), 5...Second insulator layer, 6...Third conductor layer, 7... ...Third insulator layer, 8...
・Fourth conductor layer, 9... Lead connection part of IC chip, 10... Mounting part of IC chip, 11...
...IC chip lead, 12...IC chip, 13...input/output terminal, 14...ground power supply pattern.
Claims (1)
ップに電源を供給する電源供給用パターンとを含むこと
を特徴とする多層配線基板。[Claims for Utility Model Registration] A multilayer wiring characterized by including two or more IC chips and a power supply pattern that is thick in a portion near the center and thin in a portion near the ends and supplies power to the IC chips. substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977115025U JPS5810369Y2 (en) | 1977-08-26 | 1977-08-26 | multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1977115025U JPS5810369Y2 (en) | 1977-08-26 | 1977-08-26 | multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5442971U JPS5442971U (en) | 1979-03-23 |
| JPS5810369Y2 true JPS5810369Y2 (en) | 1983-02-25 |
Family
ID=29066296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1977115025U Expired JPS5810369Y2 (en) | 1977-08-26 | 1977-08-26 | multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5810369Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5715106U (en) * | 1980-02-28 | 1982-01-26 |
-
1977
- 1977-08-26 JP JP1977115025U patent/JPS5810369Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5442971U (en) | 1979-03-23 |
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