JPS58103127A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58103127A JPS58103127A JP56202858A JP20285881A JPS58103127A JP S58103127 A JPS58103127 A JP S58103127A JP 56202858 A JP56202858 A JP 56202858A JP 20285881 A JP20285881 A JP 20285881A JP S58103127 A JPS58103127 A JP S58103127A
- Authority
- JP
- Japan
- Prior art keywords
- film
- pattern
- photoresist film
- electrode
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/039—Macromolecular compounds which are photodegradable, e.g. positive electron resists
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特にイオン注入ニーを
含む半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including an ion implantation knee.
半導体装置の動作層としては、従来、拡散層、エピタキ
シャル成長層等が用いられて来たが、動作層の中ヤリア
密度や厚さのより正確な制御を目的として、最近ではイ
オン注入層が用−られる様に＆りて１１え、を九、半導
体ウニへの表面に部分的に高中ヤリア密度のコンタクト
領域、あるいは絶縁領域とイオン注入法により形成する
技４％開発されている。その最も典型的な例がＧａＡｓ
を用−たシ■ットキ障壁ゲーＦ電界効果シランジスタ（
ＭＥ８ＦＩＴ）である。イオン注入法を用いた（ｉａＡ
ｓＭＢ８ＦＭＴの製造方法としては、例えば、従来よ）
ｌｌｌｌｉ！ＩＫ示す方法空電いられて来た。即ち、初
めに半絶縁性ＧａＡｓ基’［１１を、例えば第１のホト
レジスジ膜１２ｆマスクとしてエツチングし、パターン
位置会わせマーク１３を形成し、（第１図（−）、鋏菖
ｌのホトレジス）膜を除去した後、該位置合わ豐！−夕
を用いてイオン注入のマスクとなるパターンを第２のホ
トレジス）１１１４によシ所定の位置に形成し、次−で
、該第２のホトレジスジ膜をマスクとして、Ｓｉイオン
を加速エネルギー５Ｇ ｋｅｙ、 ドース量ｓ ｘ ｌ
ｄ”♂の条件で注入し（Ｊｌｔ８！Ｊ（ｂ））、続いて
ホトレジスト膜１４を除来し、例えば厚さ０．２声ｍの
８ｉ０．膜を被着して８００℃の水素雰囲気中で２０分
間加熱して活性化を行なった後ｆｉｓ：ｏ、膜を除去し
、次にパターン位置合わせマーク１３を用いて、例えば
ＡｕＧｅ合金、Ｎｉを順次積層したソース電極１６およ
びドレイン電極１７を所定の位置に形成しくＩ！１図（
ｃ） ） 、更に例えばＴｉ、 Ｐｉ、 Ａｕを順次積
層したシ１１ツ）キ障壁合わせマーク１３は、イオン注
入により形成された動作層１５に対してソース電極、ゲ
ート電極、ドレイン電極を位置合わせするために必要で
あり、イオン注入とは別の工程でパターン位置合わせマ
ークのみを形成する理由は、イオン注入ではＧａＡ４面
に外観上はとんど痕跡が残らず、イオン注入の工程でＧ
ａＡｓ表面にパターン位置合わせマークを形成すること
が困蝋な丸めである。このような方法では、ＭＲ８Ｆ′
ＢＴ自体の構造には直接関係のなφ位置合わせマークを
形成するために１余分のホトマスクを必要とし、また位
置合わせマーク形成のための製造工程も必要である。し
かもＭＥ８ＦＢＴの各電極は、イオン注入のパターンに
対して直接位置合わせされるべきものにもｆｌ−かわら
ず、製造ニーの最初に形成された位置合わせマークを介
して間接的［ＭＥ８Ｆｌｉ！Ｔの各電極とイオン注入の
パターンとが位置合わせされてしまい、位置合わせ精度
の低下を招く欠点があった。Conventionally, diffusion layers, epitaxially grown layers, etc. have been used as the active layer of semiconductor devices, but recently, ion-implanted layers have been used for the purpose of more accurate control of the layer density and thickness in the active layer. 9. A technique has been developed to partially form a contact region or an insulating region with a high to medium density on the surface of a semiconductor by ion implantation. The most typical example is GaAs
A field-effect silane resistor (
ME8FIT). Using ion implantation method (iaA
For example, the manufacturing method of sMB8FMT is conventional)
lllli! I received a static call about how to show IK. That is, first, a semi-insulating GaAs base 11 is etched, for example, as a mask for the first photoresist film 12f, and pattern position alignment marks 13 are formed (FIG. 1 (-), photoresist with scissors I). After removing the membrane, align the position! A pattern that will serve as a mask for ion implantation is formed at a predetermined position using a second photoresist layer (1114) using a photoresist film. , dose amount s x l
d”♂ conditions (Jlt8!J(b)), then the photoresist film 14 is removed, and an 8i0. film with a thickness of 0.2 m, for example, is deposited and placed in a hydrogen atmosphere at 800°C. After activating by heating for 20 minutes with fis:o, the film is removed, and then, using pattern alignment marks 13, a source electrode 16 and a drain electrode 17, which are successively laminated with, for example, an AuGe alloy and Ni, are placed in predetermined positions. Form it in the position of Figure I!1 (
c)) Furthermore, for example, Ti, Pi, and Au are sequentially laminated.11) The barrier alignment mark 13 aligns the source electrode, gate electrode, and drain electrode with respect to the active layer 15 formed by ion implantation. The reason why only pattern alignment marks are formed in a process separate from ion implantation is that ion implantation leaves almost no visible traces on the four GaA surfaces;
It is difficult to form pattern alignment marks on the aAs surface due to rounding. In such a method, MR8F'
One extra photomask is required to form the φ alignment mark, which is not directly related to the structure of the BT itself, and a manufacturing process for forming the alignment mark is also required. Furthermore, each electrode of the ME8FBT should be directly aligned with the ion implantation pattern, but instead of being aligned directly with the ion implantation pattern, it is indirectly aligned via alignment marks formed at the beginning of the manufacturing process [ME8Fli! Each electrode of T and the ion implantation pattern are aligned, resulting in a disadvantage that alignment accuracy is lowered.
本発明の目的は、上記従来の欠点をなくした半導体装置
の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned conventional drawbacks.
本発明によれば、半導体基板の表面を第１の膜で櫃い、
ホトレジスト膜をマスクとしてイオン注入領域およびパ
ターン位置合わせマークとなる部分を含も領域上の該第
１の膜を除去し、該第１の膜あるいは該第１の膜と該ホ
トレジスト膜の積層膜をマスタとして選択的にイオン注
入領域を形成し、該第１の膜に形成されたパターン位置
合わせマークを用いて、半導体装置の少なくとも一種類
の電極を、所定の位置に形成する工程を含むことを特徴
とする半導体装置の製造方法を得ることができる。According to the present invention, the surface of the semiconductor substrate is covered with the first film,
Using the photoresist film as a mask, the first film on the region including the ion implantation region and the pattern alignment mark is removed, and the first film or a laminated film of the first film and the photoresist film is removed. selectively forming an ion implantation region as a master, and using pattern alignment marks formed on the first film to form at least one type of electrode of the semiconductor device at a predetermined position. A characteristic method for manufacturing a semiconductor device can be obtained.
以下、図面によりＧａＡｓ ＭＢ８ＦＥＴの製造方法を
例にとって本発明を説明する。The present invention will be described below with reference to the drawings, taking as an example a method for manufacturing a GaAs MB8FET.
１１２図は本発明の一実施例を説明するための図面であ
る。図面において、２１は半絶縁性ＧａＡｓ基板、２２
はこの上に１例えば熱分解法等によ抄被着し九厚さ０．
５ｊｍのＳｉｎ、膜で、動作層およびパターン位置合わ
せマークとなる部分を含む領域の８ｉ０．膜をＮＨ，Ｐ
とＨＦの混合水溶液を用い、厚さ２μｍのポジティブ型
ホトレジスト膜２３をマスクとして完全圧除去する。次
６ｃ８ｉ０．膜２２とホトレジスト２３の積層膜をマス
クとし、例えば８ｉイオンを加速エネルギー５０ ｋｅ
ｙ、 ドーズ量２．６ Ｘ ＩＱ”ｍ”の条件で注入
した後（第２図（ｍ）、ホトレジスト膜２３を除去する
。続いて、８５０℃のＡｓ雰囲気中で１５分間所■キャ
ップレスアニールを行なって活性化を行な−、パターン
位置合わせ！−ダ２４を用いて、例えば、厚さｌｓｍの
ホトレジスト膜によりゲート電極のパターンを所定の位
置に形成し、例えば厚さ０．４＃ｍのＡ１を真空蒸着法
等によって被着した後、該ホトレジス）膜を溶解して不
要部分のＡｌｍをり７トオフし、シ日ットキ障壁ゲート
電極２６を形成する（第２図（ｂ） ）。若し、イオン
注入されていない領域のＧａＡｓ基板上にもＭ膜を設置
する必要がある場合は、該ホトレジスト膜によるゲート
電極のパターン形成ニーの後、該ホトレジスト膜によっ
て覆れない８ｉ０．膜を、例えばＮＨ４ＦとＨＦの混合
水溶液を用ψて除去し、Ａ／膜を被着すればよい。次い
で、同様にホトレジスト膜を用いたリフトオフ法によね
、ＡｕＧｅ合金、Ｎｉを順次積層した金属膜よりなるソ
ース電極２７およびドレイン電極２８を同時に形成して
ＧａＡｓＭＥ８ＦＥＴを完成した。（第２図（Ｃ））こ
のような本発明になる製造方法によれば、従来の実施例
で必要であった位置合わせ！−りのみを形成するための
工程が不要となり、製造工梅の短縮を図ることができ、
ホトマスタ数を節減することができた。また、ＭＥ８Ｆ
ＥＴの電極形成のためのパターンは、イオン注入のため
のパターンと同時に形成された位置合わせマークを用い
て位置合わせされるために、従来の実施例に比べて高い
位置合わせ精度を得ることができた。FIG. 112 is a drawing for explaining one embodiment of the present invention. In the drawing, 21 is a semi-insulating GaAs substrate, 22
1 is coated on top of this by, for example, a pyrolysis method to give a thickness of 0.
5jm of Sin, 8i0. The membrane is NH,P
Using a mixed aqueous solution of and HF, complete pressure removal is performed using the 2 μm thick positive type photoresist film 23 as a mask. Next 6c8i0. Using the laminated film of the film 22 and photoresist 23 as a mask, for example, 8i ions are accelerated at an energy of 50 ke.
After implantation at a dose of 2.6 x IQ "m" (Fig. 2 (m), the photoresist film 23 is removed. Subsequently, capless annealing is performed for 15 minutes in an As atmosphere at 850°C. Then, using the pattern alignment!-der 24, a gate electrode pattern is formed at a predetermined position using a photoresist film having a thickness of, for example, 1sm, and a pattern of a gate electrode is formed at a predetermined position by using a photoresist film having a thickness of, for example, 1sm. After depositing the photoresist film A1 by vacuum evaporation or the like, the photoresist film is melted and the unnecessary portions of Al are removed to form a barrier gate electrode 26 (FIG. 2(b)). If it is necessary to provide an M film on the GaAs substrate in areas where ions have not been implanted, after patterning the gate electrode with the photoresist film, the 8i0. The film may be removed using, for example, a mixed aqueous solution of NH4F and HF, and the A/film may be applied. Next, a source electrode 27 and a drain electrode 28 made of a metal film in which AuGe alloy and Ni were successively laminated were simultaneously formed by the same lift-off method using a photoresist film to complete a GaAsME8FET. (FIG. 2(C)) According to the manufacturing method of the present invention, alignment, which was necessary in the conventional embodiments, can be achieved! - The process for forming the ribs is no longer necessary, and the manufacturing time can be shortened.
The number of photo masters could be reduced. Also, ME8F
Since the pattern for forming the ET electrode is aligned using alignment marks formed at the same time as the pattern for ion implantation, higher alignment accuracy can be obtained compared to conventional embodiments. Ta.
なお、本実施例ではイオン注入領域が半導体装置の動作
層である場合について述べたが、イオン注入領域が高不
純物濃度のコンタクト領域の場合あるいはＢや００イオ
ン注入による絶縁領域の場合などについても同様であり
、また、例えば本実施例に於て、工程の中に他の異なる
仕様の動作領域、あるいは高不純物濃度のフンタクト領
域等を形成するためのイオン注入工柵が更に追加される
場合についても同様である。また、ＧａＡｓ Ｍｇ８Ｆ
ＥＴの製造方法についてのみ示されたが、シ曹ットキ障
壁ダイオード等の半導体装置、ある（ρは（ＧａＡｓ以
外の半導体についても同様に本発明が適用されることは
言うまでもない。Although this embodiment describes the case where the ion implantation region is an active layer of a semiconductor device, the same applies to the case where the ion implantation region is a contact region with a high impurity concentration or an insulating region formed by B or 00 ion implantation. In addition, for example, in this embodiment, in the case where an ion implantation fence is further added to form an operating region with different specifications or a high impurity concentration contact region, etc. in the process. The same is true. Also, GaAs Mg8F
Although only a method for manufacturing an ET has been described, it goes without saying that the present invention is similarly applicable to semiconductor devices such as silicon barrier diodes and other semiconductors other than GaAs.
第１図は従来のシッットキ接合ゲート電解効果トランジ
スタの製造方法ｔａ明するだめの図面、第２図は本発明
の詳細な説明するための図面アある。図面において、１
１．２１は半絶縁性ＧａＡｓ基板、２２は８ｉ０．膜、
１２．１４．２３はホＦレジスト膜１３．２４はパター
ン位置合わせマーク、１５．２５はイオン注入領域、１
８．２６はゲート電極、１６．２７はソース電極、１７
．２８はドレイン電極を示す。
慄 １ 目
５FIG. 1 is a diagram for explaining a conventional method of manufacturing a Schittky junction gate field effect transistor, and FIG. 2 is a diagram for explaining the present invention in detail. In the drawing, 1
1.21 is a semi-insulating GaAs substrate, 22 is an 8i0. film,
12.14.23 is a photo-F resist film 13.24 is a pattern alignment mark, 15.25 is an ion implantation area, 1
8.26 is the gate electrode, 16.27 is the source electrode, 17
．． 28 indicates a drain electrode. Horror 1 Eye 5
Claims (1)
をマスクとしてイオン注入領域およびパターン位置合わ
せマークとなる部分を含む領域上の該ａｌｌの膜を除去
し、該＃１１の膜あるーは該＠１の膜と該ホトレジスト
膜の積層膜をマスタとして選択的にイオン注入領域を形
成し、該第１の膜に形成されたパターン位置合わせ！−
夕を用いて半導体装置の少なくとも一穏ＩＩＯ電極を所
会の位置に形成するニーを含むことを特徴とする半導体
装置の製造方法。Using the first film and the #11-1 photoresist film as a mask, the surface of the semiconductor substrate is removed from all the films on the region including the ion implantation region and the part that will become the pattern alignment mark, and the #11 film is removed. Selectively form ion implantation regions using the laminated film of the @1 film and the photoresist film as a master, and align the pattern formed on the first film! −
1. A method of manufacturing a semiconductor device, comprising: forming at least one intermediate IIO electrode of the semiconductor device at a predetermined position using a metal plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56202858A JPS58103127A (en) | 1981-12-16 | 1981-12-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56202858A JPS58103127A (en) | 1981-12-16 | 1981-12-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58103127A true JPS58103127A (en) | 1983-06-20 |
Family
ID=16464356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56202858A Pending JPS58103127A (en) | 1981-12-16 | 1981-12-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58103127A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5001076A (en) * | 1987-10-23 | 1991-03-19 | Vitesse Semiconductor Corporation | Process for fabricating III-V devices using a composite dielectric layer |
-
1981
- 1981-12-16 JP JP56202858A patent/JPS58103127A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5001076A (en) * | 1987-10-23 | 1991-03-19 | Vitesse Semiconductor Corporation | Process for fabricating III-V devices using a composite dielectric layer |
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