JPS58102545A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS58102545A
JPS58102545A JP20091781A JP20091781A JPS58102545A JP S58102545 A JPS58102545 A JP S58102545A JP 20091781 A JP20091781 A JP 20091781A JP 20091781 A JP20091781 A JP 20091781A JP S58102545 A JPS58102545 A JP S58102545A
Authority
JP
Japan
Prior art keywords
foil
circuit
hybrid
substrate
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20091781A
Other languages
Japanese (ja)
Inventor
Norihiko Nagai
長井 紀彦
Sumio Komi
小見 澄男
Toshimasa Kobayashi
敏正 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP20091781A priority Critical patent/JPS58102545A/en
Publication of JPS58102545A publication Critical patent/JPS58102545A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1617Cavity coating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components

Abstract

PURPOSE:To obtain a structure resistant to external noises with high reliability, by forming a part or the whole of a hybrid IC in a structure coated with conductive metal. CONSTITUTION:On an alumina substrate 10 wherein a circuit is formed of a thin film of a thick film, electronic parts 11 of a transistor, an IC, etc. are mounted and soldered to the circuit, and a Cu foil 13 is adhered on the back surface of the substrate 10. A lead frame 12 is connected to the circuit at one side end part of the substrate 10, and the entire body is protected by coating with the resin 14 such as epoxy resin. When the magnetic field is applied to the Cu foil 13 and inversed at a high frequency, the electromagnetic induction from a noise source which exists in the right direction, because of being erased by the magnetic field generated by the eddy current on the Cu foil 13 generated according to the Lenz's law, is not passed through the Cu foil, and accordingly the influence given to the hybrid IC is cut off or reduced. In a static aspect, the hybrid IC is shielded by the Cu foil 13 and becomes difficult to be subjected to noise hindrances.

Description

【発明の詳細な説明】 本発明は、混成集積回路の構造に関する。[Detailed description of the invention] The present invention relates to the structure of hybrid integrated circuits.

従来、混成集積回路は、薄膜又は厚膜で回路が形成され
たアルミナ基板に、電気部品および外部リードフレーム
を牛田付けし、基板全体をエポキシ樹脂で保II″:I
−テングするか、或はモールド形成されたケースに入れ
てシリコン樹脂てポツティングし友構造が一般的である
Conventionally, hybrid integrated circuits are manufactured by attaching electrical components and external lead frames to an alumina substrate on which a circuit is formed using a thin film or thick film, and then protecting the entire board with epoxy resin.
- A common structure is to attach the device to a protrusion or to place it in a molded case and pot it with silicone resin.

上述の従来の混成集積回路は、トランス等の高電界を発
生する電気部品の近傍に配設された場合に、電気部品の
発生する電界の影響を受は易く、誤動作するおそれがあ
る。すなわち、外部電界雑音に弱いという欠点がある。
When the above-described conventional hybrid integrated circuit is placed near an electric component such as a transformer that generates a high electric field, it is easily affected by the electric field generated by the electric component and may malfunction. That is, it has the disadvantage of being weak against external electric field noise.

また、従来の混成集積回路を装置に組込む場合は上記欠
点により配電上の制約が大きく、装置を小型化すること
が困難である。
Furthermore, when a conventional hybrid integrated circuit is incorporated into a device, the above-mentioned drawbacks impose severe constraints on power distribution, making it difficult to downsize the device.

本発明の目的は、上述の従来の欠点を解決し、外部雑音
の影響を受は難い混成集積回路管提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to overcome the above-mentioned drawbacks of the prior art and to provide a hybrid integrated circuit tube that is less susceptible to external noise.

本発明の混成集積回路は、電導性金属膜又は箔でその周
囲の全部又は一部を覆うことにより上記目的を達成する
ものである。
The hybrid integrated circuit of the present invention achieves the above object by covering all or part of its periphery with a conductive metal film or foil.

外部雑音の影響を除去するためには、一般に電磁遮蔽お
よび静電遮蔽1行なわなければならない。
In order to eliminate the influence of external noise, electromagnetic shielding and electrostatic shielding must generally be performed.

電磁値藪は、一般に高透磁率の磁性体を用いて充分な厚
さの遮蔽を要するから、混成集積−路のような微細なも
のに施すことは容易でなく、かつ不経済である。一方、
混成集積回路#i、一般に低周波雑音の誘導で祉誤動作
しないが高周波雑音によっては誤動作するものが多い。
Since electromagnetic shielding generally requires a sufficiently thick shield using a magnetic material with high magnetic permeability, it is difficult and uneconomical to apply it to minute objects such as hybrid integrated circuits. on the other hand,
The hybrid integrated circuit #i generally does not malfunction due to induction of low frequency noise, but many malfunction due to high frequency noise.

本発明はこの点に着目してなされたものであって、単に
電導性金属膜又は箔で覆う仁とによシ、静電的導蔽のみ
彦らず電磁的遮蔽効果tも生じさせ外部雑音の影響を防
ぐものである。
The present invention has been made with attention to this point, and the method of simply covering with a conductive metal film or foil does not only provide electrostatic conduction but also generates an electromagnetic shielding effect and reduces external noise. This is to prevent the effects of

次に、本発明について、図面を参照して詳細に説明する 第1図は、本発明の一実施例を示す断面図であり、シン
グルインラインの混成集積回路に適用したものである。
Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing one embodiment of the present invention, which is applied to a single in-line hybrid integrated circuit.

すなわち、薄膜又は厚膜で回路が形成されたアルミナ基
板lOに、トランジスタ。
That is, a transistor is formed on an alumina substrate 10 on which a circuit is formed using a thin film or a thick film.

IC等の電気部品11f:搭載し、所要個所を回路に半
田付けし、基板lOの裏面に銅箔13が貼布されている
。また、リードフレーム12は基板10の一儒端郁にお
いて上記回路の所要個所に接続されている。そして全体
をエポキシ尋の樹脂14で保鏝コーティングした構造で
ある。本実施例では、%に図中右方向に存在する雑音源
からの電磁誘導は、磁束が銅箔13を貫通し、高い周波
数で反転するときけ、レンツの法則によって生ずる銅箔
13上の渦電流で生ずる磁束によって打消されるため鋼
箔を貫通せず、混成集積回路に与える影響は迩断又Fi
軽減される。静電的には勿論銅箔lOによって遮蔽され
ている。すなわち、混成集積回路が雑音妨害を受は離く
なるという効果がある。
Electrical components 11f such as ICs are mounted, soldered to circuits at required points, and copper foil 13 is pasted on the back surface of the board 1O. Further, the lead frame 12 is connected to the required portions of the circuit at one end of the substrate 10. The entire structure is coated with epoxy resin 14. In this example, the electromagnetic induction from the noise source present in the right direction in the figure is caused by the eddy current on the copper foil 13 caused by Lenz's law when the magnetic flux penetrates the copper foil 13 and reverses at a high frequency. Because it is canceled by the magnetic flux generated by the magnetic flux, it does not penetrate the steel foil and has no effect on the hybrid integrated circuit.
Reduced. Of course, it is electrostatically shielded by the copper foil lO. In other words, there is an effect that the hybrid integrated circuit is less susceptible to noise interference.

第2図は、本発明をデュアルラインノ(ツケージ形の混
成集積回路に適用し*実施例を示す。こO場合は、基板
21の両側端部からリードフレーム21が外部へ導出さ
れていて、基板21はモールド成形されたケース22で
覆われ、シリコン等の樹脂23てポツティングされてい
ることは従来と同様であるが、ケース220内面に銅メ
ッキ膜24が無電解メッキによって形成されている。こ
の場合も前述と同様な効果を有する。
FIG. 2 shows an example in which the present invention is applied to a dual-line hybrid integrated circuit. In this case, the lead frame 21 is led out from both ends of the substrate 21. The substrate 21 is covered with a molded case 22 and potted with a resin 23 such as silicon, as in the conventional case, but a copper plating film 24 is formed on the inner surface of the case 220 by electroless plating. This case also has the same effect as described above.

上述の銅箔又は銅メッキ膜に代えて、アル建等の電気伝
導率の高い金属を用いても良い。を良、1111図に示
した銅箔はエポキシ樹脂の外側にもうけても棗く、第2
図に示し要綱メッキはケースの外側又はケース全体に行
なってもよい。回路全体を囲むことが望ましいことは勿
論である。
Instead of the above-mentioned copper foil or copper plating film, a metal with high electrical conductivity such as aluminum may be used. The copper foil shown in Figure 1111 is good even if it is placed on the outside of the epoxy resin.
The plating shown in the figure may be applied to the outside of the case or to the entire case. Of course, it is desirable to surround the entire circuit.

以上のように、本発明においては、混成集積回路〇一部
又は全部を導電性金属で覆った構造とし  ゛たから、
回路の誤動作を与えるような高周波妨害雑音から遮蔽さ
れ、外部雑音に強く信頼性の高い回路とする効果がある
As described above, in the present invention, since the hybrid integrated circuit has a structure in which part or all of it is covered with conductive metal,
This has the effect of making the circuit resistant to external noise and highly reliable, as it is shielded from high-frequency interference noise that could cause circuit malfunction.

41111F+0簡JIIIl明 1111図は本発明の一実施例を示す断面図、第2II
轄本発110他O実施例を示す断面図である。
41111F+0Simplified JIIIL 1111 is a sectional view showing one embodiment of the present invention, No. 2II
FIG. 2 is a sectional view showing an embodiment of the central office 110;

WJにおいて、10.21・・・アルミナ基板、11・
−電気部品、12・・・リードフレーム、13−銅箔、
!4−・エポキシ樹脂、22・・・ケース、23川シリ
クン樹脂、24−・・鋼メッキ膜。
In WJ, 10.21... alumina substrate, 11.
- Electrical component, 12... Lead frame, 13- Copper foil,
! 4--Epoxy resin, 22--Case, 23-Silicon resin, 24--Steel plating film.

代理人 弁理士 住 1)俊 宗 第1図 第2図Agent: Patent attorney: 1) Sou Toshi Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 電導性金属膜又は箔で同罪の全部又社一部が覆われたこ
と1%像とする混成集積回路。
A hybrid integrated circuit that is entirely or partially covered with a conductive metal film or foil is considered to be 1%.
JP20091781A 1981-12-15 1981-12-15 Hybrid integrated circuit Pending JPS58102545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20091781A JPS58102545A (en) 1981-12-15 1981-12-15 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20091781A JPS58102545A (en) 1981-12-15 1981-12-15 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS58102545A true JPS58102545A (en) 1983-06-18

Family

ID=16432417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20091781A Pending JPS58102545A (en) 1981-12-15 1981-12-15 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS58102545A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6058646A (en) * 1983-09-12 1985-04-04 Toshiba Corp Hybrid integrated circuit
JPS622557A (en) * 1985-06-27 1987-01-08 Mitsubishi Electric Corp Method for preventing static breakdown of semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4821569B1 (en) * 1968-10-17 1973-06-29
JPS5324449B1 (en) * 1967-08-14 1978-07-20
JPS567349B1 (en) * 1968-02-26 1981-02-17

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5324449B1 (en) * 1967-08-14 1978-07-20
JPS567349B1 (en) * 1968-02-26 1981-02-17
JPS4821569B1 (en) * 1968-10-17 1973-06-29

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6058646A (en) * 1983-09-12 1985-04-04 Toshiba Corp Hybrid integrated circuit
JPS622557A (en) * 1985-06-27 1987-01-08 Mitsubishi Electric Corp Method for preventing static breakdown of semiconductor device
JPH0451060B2 (en) * 1985-06-27 1992-08-18 Mitsubishi Electric Corp

Similar Documents

Publication Publication Date Title
US20060152913A1 (en) Method and apparatus for reducing electromagnetic emissions from electronic circuits
FI950182A0 (en) Electromagnetic interference suppressor with low electromagnetic radiation and reflection and electronic device
US4737597A (en) Shield case
JPS58102545A (en) Hybrid integrated circuit
SG96612A1 (en) Electronic component of a high frequency current suppression type and bonding wire for the same
JPH073195U (en) Exterior structure of hybrid integrated circuit parts
JPH06326218A (en) Semiconductor device
TW255091B (en) A hybrid integrated circuit device and process of manufacturing thereof
JPH0613496Y2 (en) Clamp sensor
TW263650B (en) An electronic apparatus and method suppressing its noise
JPS6439100A (en) Packaging method of semiconductor integrated circuit
JPH021920Y2 (en)
JP2002158317A (en) Low noise heat dissipation ic package and circuit board
JP3463189B2 (en) Electromagnetic interference suppressor, method of fixing electromagnetic interference suppressor, and components and equipment using them
US6414383B1 (en) Very low magnetic field integrated circuit
JP2833049B2 (en) Printed wiring board
JPH0494196A (en) Electronic circuit board
JP2867710B2 (en) Plastic pin grid array
JPH0526800Y2 (en)
JPS59186397A (en) Hybrid integrated circuit
JPS5971227A (en) Method of mounting lead relay
JPS6381899A (en) Cubicle equipment
JPS57194133A (en) Wiring device for car
JPH02288083A (en) Ic socket
JPH02159800A (en) Electromagnetic shield body