JPS58102392A - Read-only memory control circuit - Google Patents

Abstract

PURPOSE:To obtain a device of simple constitution which provides relatively high-speed processing by applying a synchronizing signal to a decoder through an inverter and a differentiating circuit, and selecting an optional read-only memory corresponding to an address signal. CONSTITUTION:A synchronizing signal obtained by a central processing unit is applied to a decoder through an inverter and a differentiating circuit, and this decoder accesses an optional read-only memory corresponding to an address signal from the central processing unit to make the access period of the read- only memory longer than the synchronizing signal period. For example, a synchronizing signal is sent out of the central processing unit 1 from a terminal phi2 and inputted to the inverter 2, which performs phase inversion to apply the resulting output signal to a terminal -CE of the decoder 3 of the differentiating circuit 8. Then, the decoder 3 operates read-only memories 4-7 selectively in accordance with the address signal from the central processing unit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read-only memory control circuit that controls a read-only memory by using a central processing unit with a high operating speed. Its purpose is to provide superior read-only memory that can be accessed.

Generally, when a central processing unit is used to control a read-only memory, it is often configured as shown in FIG. In FIG. 1, reference numeral 1 denotes a central processing unit that executes program processing, and is configured such that when a synchronizing signal appears from a terminal φ2, the phase of this signal is inverted by an inverter 2 and input to a small terminal of a decoder 3. The decoder 3 is enabled by the synchronization signal applied to the terminal d, and is configured to select any of the synchronous read-only memories 4 to 7 in response to an address signal from the central processing unit 1. Therefore, when a synchronization signal appears from the terminal φ2 of the central processing unit 1, the memories 4 to 7 selected by the decoder 3 are enabled, and the information stored therein is imported into the central processing unit 1 via the data bus. It will be.

Incidentally, in this case, if the operating speed of the central processing unit 1 is made relatively high, there is a problem that a large capacity read-only memory cannot be used as the read-only memory.

In other words, since a large capacity read-only memory has a relatively long access time and a relatively low operating speed, the read-only memory cannot keep up with the operating speed of the central processing unit 1, and accurate operation cannot be expected. There was a problem with it disappearing.

The present invention eliminates the above-mentioned conventional drawbacks and provides an excellent read-only memory control circuit that has a simple configuration and is capable of relatively high-speed processing.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A read-only memory control circuit according to the present invention will be described below with reference to drawings of an embodiment. FIG. 2 is a schematic block diagram of one embodiment of the read-only memory control circuit of the present invention, in which numerals 1 to 7 are the same as those shown in FIG. 8 is a differential circuit connected to the output example of the inverter 2, and as shown in FIG.
, and a capacitor 1Q.

In the above embodiment, it is assumed that the synchronization signal outputted from the terminal φ2 of the central processing unit 1 is as shown in FIG. 4a. In this case, the output of the inverter 2 will be as shown in FIG. Therefore, the output of the differentiating circuit 8 becomes as shown in FIG. 4C, which is applied to the CE terminal of the decoder 3. By the way, in this case, since the decoder 3 has the threshold level SL, it is substantially the same as dK in FIG.
Works as shown. That is, the decoder 3 is enabled during the period B when the level is low in FIG. 4d, and the selected one of the read-only memories 4 to 7 becomes operational.

In FIG. 4, time charts 1-1f of the address signals output from the central processing unit 1 are time charts of the tapes output from the read-only memories 4-7.

As is clear from FIG. 4, when the differentiating circuit 8 is not provided after the inverter 2 and the output of the inverter 2 is applied to the IT decoder 3, the cutoff for enabling the decoder 3 is determined by the synchronization signal period. However, it becomes A.”-
In the above embodiment, since the differentiating circuit 8 is provided after the inverter 2, the decoder 3 is enabled.The brightness can be changed from A in Figure 4 to B in Figure 4d. , the access period of the read-only memories 4 to 7 is lengthened accordingly, so that even the read-only memory having a slow operating speed can sufficiently correspond to the operating speed of the central processing unit 1. Therefore, according to the above embodiment, even a read-only memory having a relatively large capacity and a slow operating speed can be controlled with sufficient accuracy, and is extremely advantageous in practice.

Note that the address is normally resolved before the fall of the synchronization signal, and therefore the address period is almost never inserted into the memory access period.

As is clear from the above embodiments, the control device of the present invention converts the synchronization signal obtained by the central processing unit into an inverter,
It is configured to be applied to 6 terminals of the decoder via a differentiating circuit, and the decoder is enabled earlier than before, and the selected read-only memory can also be accessed for a longer period of time than before. It has the advantage of being auspicious when it reaches this state, and being able to respond to faster actions.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a conventional read-only memory control circuit, FIG. 2 is a schematic block diagram of an embodiment of the read-only memory control circuit of the present invention, and FIG. 3 is a detailed electrical diagram of the same essential parts. The wiring diagram in FIG. 4 is an explanatory diagram of the operation of the circuit. 1 Central processing unit, 2...-inverter, 3-decoder, 4-7--read-only memo 1)-18--differentiating circuit. Name of agent: Patent attorney Toshio Nakao (1 person)
(Mo ＼ ＼ ＼ ＼ 0] 麩Fig. 4, 3I] 1 ] I L -J

Claims (1)

[Claims] The synchronization signal obtained by the central processing unit is transferred to an inverter,
The signal is applied to a decoder via a differentiating circuit, the decoder selects an arbitrary read-only memory according to the address signal from the central processing unit, and the access period of the read-only memory is made longer than the synchronization signal period. read-only memory control circuit.