JPS58101546A - Serial transmission system - Google Patents

Abstract

PURPOSE:To avoid the effect of noise, by coding logical 1, logical 0, and a start bit, and a code consisting of logical 0 and logical 1, and discriminating the recognition of codes from the combination of the consecution time of logical 0 and logical 1. CONSTITUTION:An input signal code is inputted to a terminal 1. In inputting a clock to a terminal 2, each output of a shift register 3 is as shown in waveforms c-k. Each output of 3-input decision by majority circuits 4, 5, 6 is as shown in waveforms l-n, and a waveform at an OUT3 of a decoder 7 is as an output (p). The output of an NOR gate 14 is as an output (0), and an output of a gate 8 goes high in the timing when the entire start code is read in the shift register 3, and then becomes an output (q). A counter 10 which takes the pulse of the output (q) as a start signal and frequency-divides the output (b), starts count and an output of a gate 11 is as shown in (r). In the output (r), the output of the OUTs 1, 2 of the decoder 7 is sampled via gates 12, 13, and the result is distributed to FFs 191-19n at selectors 17 and 18.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a serial transmission system in communication that takes measures against noise.

The conventional meko type transmission system will be described next. Figure 1 is a wiring diagram for the serial transmission system, and Figure 2 is a schematic diagram of the receiving circuit in the conventional serial transmission system, where T is the transmitting side, R is the receiving side,
L is a signal line, SR is a shift renostar, CI is a counter, G is a gate, C24 counter, and 0 is an oscillation circuit. The operation will be explained using the example data transfer time chart shown in FIG. Figure 3 (a) is an example of the signal line waveform (output waveform on the transmitting side) during data transfer, (b) is the signal line waveform on the receiving side, and (C) is the same after sampling on the receiving side. Indicates read data. As shown in the figure, the receiving side detects a change from the "H" logic level to the "L" logic level of the signal line L, and regards this detection as the start of transmission of the transmitting side, and the counter C1 starts counting. However, after the to time, the input signal line is sampled with the output of the counter C1, and if it is at the @L' logic level, the sampling data in the 2to time period is further regarded as received data.

Therefore, if noise is added to the signal line L, the receiving side may misinterpret it as the start of transmission, and if noise is added to the sampling after the 7fL1 pit, there is a possibility of reading incorrect data. there were.

In order to eliminate such conventional drawbacks, the present invention provides 1",
'0# and the start pit are further encoded into a code consisting of "0" and "l", and the recognition of the code is determined by "0" and "1".
A communication system that is resistant to noise can be obtained by determining the combination of the durations of ``.'' Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram of a receiving circuit showing a first embodiment of the serial transmission system of the present invention, and is an example of application to remote control for turning on and off a plurality of loads using a single signal line. In the figure, 1 is the data input terminal of the shift register 3, 2 is the clock terminal into which the clock of the shift register 3 is input, and 3 is the data input terminal of the shift register 3.
is a 9-stage shift register; 4. ．． 5.6 is a majority circuit with 3 people each, 7 is 3 of IN7, IN2, INJ
Input terminal and 0UTI.

It has three output terminals: OUT 2 and OUT J, and the first
A truth table decoder as shown in the table, 8, 11, 12° 13 is f-to, 10 is a count start instruction input 9
It is a forward counter. 14 is a fugate. 15 is an oscillator, 16 is a frequency divider circuit having a division start instruction input, 17
201 is a selector that distributes the output of f-) 72 to Rδ frig-flops r93 to 19n based on the input from the frequency dividing circuit 16; ~20n is the driver, 211~2
1n is a load. The first three outputs of the shift register 3 are input to the majority circuit 4, the next three outputs are input to the majority circuit 5, the remaining three outputs are input to the majority circuit 6, and the output of the majority circuit 4 is INJ of decoder 7
The output of the majority circuit 5 is connected to the same <IN2, and the output of the majority circuit 6 is connected to the same (, INS. The 4th and 6th inputs are input, and the output thereof is inputted to r-to 8. - The remaining inputs to gmut 8 are input from OUT 3 of decoder 7.

The output of the gate 8 is the 9-ary counter 10 and the frequency divider circuit 1.
6, and the same clock as that of the shift register 3 is inputted to the clock of the 9-ary counter 10 and the frequency dividing circuit 16. The 9-ary output of the clock of the 9-ary counter 1o is input to the dart 1), and the same clock as that of the shift register 3 is input to the remaining inputs. gate 1
The output of gate 12 is connected to the input of gate 12゜1'''3, and the remaining input of gate 12 is connected to OUT 2 of decoder 7.
OUT J of the decoder 7 is input to the remaining inputs of the gate 13, respectively.

The output of gate 12 is input to selector 17, and selector 17 outputs the input from gate 2 to only one output terminal based on the input from counter 16.

Further, the selector 18 outputs the input from the gate 13 to only one output terminal based on the input from the counter 16. The outputs of the selector 12 are respectively Vsflip:-flo! 191
.about.19n, and the output of the selector 18 is connected to the R terminal of R.delta. The R/S Frigg Frog 19. ~19n
The Q outputs of each of the drivers 201 to 20n K are connected to the respective loads 211 to 21n.

Next, to operate this, we need to create a series of waveforms as shown in Figures 6 and 4 using the code shown in Figure 5.
Assume that an input is made to data input terminal 1 in the figure.

On the other hand, each output of the 9-stage shift register of the shift register 3 becomes the waveform shown in (c) to (k) in FIG. 6 due to the clock of synchronization t inputted from the clock terminal 2.

In addition, each output of the three-man power majority circuits 4, 5.6 is outputted according to the input state from the shift register 3 (1) in FIG.
), ←), (n), and decoder 2
The waveform of OUT 3 is as shown in the output ω) in FIG.

The output of the NOR gate 14 becomes the output (0) in FIG. 6, and the output of the gate 8 becomes "H#" at the timing when the entire start coat 9 is read into the shift register 3, and from then on, the output becomes "H#" as shown in the output (q). With this output (q) pulse as a start signal, the 9-ary counter 10 whose frequency is to be divided by the output waveform (b) starts counting.
The output of the gate 11 is as shown in output (r) in FIG.

Output 7]/l of this gate 11 is the OUT of decoder 7
The outputs of gates 12 and 13 are sampled through dart 12.13, and the outputs of gates 12 and 13, which are the S/f Kling results, are sent to selector 17.18.
~19n. It should be noted that the start/bring timing is performed at the timing when the entire code is read into the shift register.

The distribution destination depends on the contents of the frequency divider circuit 16, and by starting the count of the frequency divider circuit 161fJ at the output signal of the r-to-8, a uniquely determined distribution order is executed.

Therefore, in the input order of input 11" and "O" codes, they are input to Rβ free and ! frogs 191 to 19n in a unique distribution order, and turn on or off each Q output. In this embodiment, the welfare input code Load on PH 21..21.,
It turns on and off in the order of -21n.

Thus, in the first embodiment, each bit of the "1m" or "O" code consisting of three bits from K and G generates the sampling pulse shown in output (1) in FIG.

Three majority circuits each consisting of 3 bits 4゜5.6
Since it can be sampled at the time when it is independently input to each bit, it is possible to recognize the level at which the time width of each bit is the same as the one above as the λ data, determine the code, and process the single person data, that is, the present embodiment. In the case of load 211~2 J
Since n is turned on and off, even if noise is added to the serially input data, it is possible to remove the noise. Furthermore, even when there is a lot of noise, it is not possible to determine the code "1"-0, so there is an advantage that the load is not turned on or off.

FIG. 7 is a block diagram showing a second embodiment of the present invention. In the first embodiment, the constituent bits of each code are divided into three equal parts, and each bit is passed through a majority voting circuit as "l#,"0. However, the second embodiment is a further improvement on this, and even if the majority circuits 4, 5゜6 and NOR gate 14 in Fig. 4 are replaced with decoders, the same noise removal effect is obtained. In the figure, parts having the same functions as those in Figure 4 are given the same reference numerals.In the figure, 31 is a 15-stage shift register 32, 34, 36 is a 5-bit input decoder, etc.
``1'' is output when 4 bits or more are 10''. 3!
j, 3F, and 37 are 5-bit input decoders, and when 4 or more bits are "l#", "1" is output.

38 is a decoder according to the truth table shown in Table 2, 39 is 1
It is a quinary counter, and the first stage 5 outputs of the shift register 31 are sent to the decoders 32 and 33, and the middle stage 5 outputs are sent to the decoder 3.
4.・The 5 outputs in the rear stage of 35 are decoded! 36, 37, respectively, and are connected to the inputs of decoders 32, 33, 34, 35 .
3”ij!a Each output is INJB, I of the decoder 38, respectively.
INIA, IN'B, lN2ABIN3B, IN,? A
The output OUT 3 is input to the counter start terminal of the counter 39 and frequency divider circuit 40. Other details are the same as in Figure 4.

Next, to operate this, use the code shown in Fig. 5 to send a series of waveforms as shown in Fig. 8 to the data input terminal 1 in Fig. 7. If a waveform like this is input to the clock terminal 2 in Fig. 7, the shift register 3
The 15 outputs of 1 are each output from the first stage as shown in Fig. 8 (c),
(to + (e) p (f) , (g) p (
h) , (t) e (j).

(h), (1) #), (n), (o)
, (p), (q), and the decoder 32 in FIG.

The outputs of 37 are (,), (1), (,), (v
), (→, (X), and the output of the decoder 38 is (y), (,), (a). The output of OU'l'3 is 14/1 of the entire start code. 15 is read into the shift register meta 3, and is input to the counter 3f1 frequency dividing circuit 40, which instructs the counter 39 and frequency dividing circuit 40 to start.
The counter 39 starts dividing the waveform shown in FIG. 8 by 15.

The output is ANDed with the waveform (b) by the gate 11 to become the waveform (c). In this waveform (c), the time length is 11'' code or "0#" code, and when the 14//15 is read, the output of the decoder 38 is sent to the gates 12 and 13.
will be sampled through. Therefore, the output of the gate 12 in FIG. 7 becomes the waveform shown in FIG. 8), which becomes the mother pulse when the "1" code is detected. Further, the output of the gate 7J in FIG. 7 has a waveform (E) in FIG. 8, which indicates that a "0" code has been detected. The subsequent processing is the same as in the first embodiment.

After detecting the start code in this way, input terminal 1 in Figure 7
Even if noise is added to the decoder 32', 33°34.35
．． Since the output of 36 and 37 is not output unless it is 4 bits or more "O" or "l#", the decoder 38 does not detect the "0" code or the "''bi code. That is, if noise is present, the received data is advantageously ignored.

Also, if noise is added to input terminal 1 while receiving the start code and incorrect data is read into 1 bit of shift register 3, the entire start code will be 15/l 5.
Since the start code is found when the code is read into the shift register 3, the subsequent "0" or 1-bit code is sampled when 15/15 of it is read into the shift register 31, which causes further noise. It will be strong.

FIG. 9 is a block diagram showing a third embodiment of the present invention,
Second. Decoder 4 is used instead of decoders 32, 34, 37 and 38 of FIG. 7 used to obtain OUT 3 in the embodiment of FIG.
Decoders 37, 34, 32 used to obtain OUT 1 of decoder 38 in FIG.
．． Decoders 44,45,46,47 are used instead of 38, and decoders 44,4° are used instead of decoder 37°35,32 used to obtain OUT 2 of decoder 38 in FIG.
The configuration uses 5,46°47, and is particularly resistant to noise read into the shift register 3 at the time of one sampling of the 'bi, Ilo@ code. Note that the decoders 41 and 42 output ``1#'' when 4 bits or more are ``0'', the decoder 43 outputs 11'' when 4 bits or more are ``1#'', and the decoder 44 . ．． 45.46 is the majority circuit,
The decoder 47 is a decoder that satisfies the truth table shown in Table 3.
The decoder 48 is a decoder that satisfies the truth table shown in Table 4.

As explained in detail above, the present invention determines the logic level based on the results of sampling received dinotal data multiple times at time intervals smaller than the time width of the smallest bit constituting the data, and determines the code. Therefore, even when noise is present on the signal line, it has the ability to remove noise in logic circuit processing, and is highly effective when used in communication systems in noisy environments.

[Brief explanation of the drawing]

Figure 1 is a connection diagram for the serial transmission system, Figure 2 is a block diagram of the receiving circuit for the conventional serial transmission system, Figure 3 is the time chart for data transfer, and Figure 4 is the serial transmission system of the present invention. A block diagram of a receiving circuit showing a first embodiment of
FIG. 5 is a time chart of a code according to an embodiment of the present invention.
6 is the time chart of FIG. 4, the 7th tooth is a block diagram showing the second embodiment of the present invention, FIG. 8 is the time chart of FIG. 7, and FIG. FIG. 2 is a block diagram showing an example. 1...Data input terminal, 2...Clock terminal, 3.
...Shift register, 4,5.6...Majority circuit, 7
... Decoder, 8 ... Gate, 10 ... Counter, 11゜12.13 ... Gate, 14 ... NOR gate, 15 ... Oscillator, 16 ... Branch circuit, 17. ．．
1B...Selector, 191-19n...&4 Free,
Gufurotsuno, 201~20n...driver, 211~
21n...Load, 31...Shift register, 32,
33, 34, 35, 36° 37.38...decoder,
39... Counter, 40... Frequency dividing circuit, 41 to 48
···decoder. Figure 1 Figure 2 - Figure 3 Figure 4 Figure 5 0 no C's) C') (N) Figure 9 Procedural amendment form) Commissioner of the Japan Patent Office 1 Display of the case 1982 Patent Application No. 199506 2 Title of the invention Serial transmission system 3 Case of the person making the amendment Relationship with Patent Application Personnel Office (
〒-105) 1-7 Toranomon, Minato-ku, Tokyo No. i12 Name (029) Representative of Oki Electric Industry Co., Ltd.
Masao Miyake (#1 or 1 person) 4 Agent address (〒105) 5-8-4 Toranomon, Minato-ku, Tokyo 5-5 Toranomon, Minato-ku, Tokyo Nakaon pages 4, 10, and 14 of the statement of the date of the amendment order Correct as shown in the attached sheet.

Claims (1)

[Claims] In the serial transmission system, the binary numbers “l#” and “0” are further encoded into codes consisting of multiple “1#” and “0#”,
On the receiving side, there is a multi-pit storage circuit that sequentially stores input data, a decoder that decodes the output, a counter that starts counting at the output of the decoder, and the output of the decoder is sampled using the output of the counter. A serial transmission method characterized by: