JPS58101314U - Clock pulse generation circuit - Google Patents

Clock pulse generation circuit

Info

Publication number
JPS58101314U
JPS58101314U JP19760281U JP19760281U JPS58101314U JP S58101314 U JPS58101314 U JP S58101314U JP 19760281 U JP19760281 U JP 19760281U JP 19760281 U JP19760281 U JP 19760281U JP S58101314 U JPS58101314 U JP S58101314U
Authority
JP
Japan
Prior art keywords
circuit
clock pulse
output
generation
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19760281U
Other languages
Japanese (ja)
Other versions
JPH0317481Y2 (en
Inventor
田中 和佳
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP19760281U priority Critical patent/JPS58101314U/en
Publication of JPS58101314U publication Critical patent/JPS58101314U/en
Application granted granted Critical
Publication of JPH0317481Y2 publication Critical patent/JPH0317481Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はディジタル・オーディオディスクの信号フォー
マットを示す図、第2図は本考案によるクロックパルス
発生回路の一実施例を示す回路図、第3図a ”’ j
、第4図a〜j、第5図a−jは第2図に示す回路の各
部動作波形図である。 1・・・負成分カット回路、2・・・微分回路、3・・
・負成分カット回路、4・・・スロープ形成回路、5・
・・プルアップ回路、6・・・ラッチ回路、7・・・差
動回路、訃・・ローパスフィルタ、9・・・電圧制御型
可変発振器。
Fig. 1 is a diagram showing the signal format of a digital audio disc, Fig. 2 is a circuit diagram showing an embodiment of the clock pulse generation circuit according to the present invention, and Fig. 3 is a diagram showing the signal format of a digital audio disc.
, FIGS. 4a-j, and 5a-j are operation waveform diagrams of each part of the circuit shown in FIG. 2. 1... Negative component cut circuit, 2... Differential circuit, 3...
・Negative component cutting circuit, 4... slope forming circuit, 5.
...Pull-up circuit, 6...Latch circuit, 7...Differential circuit,...Low pass filter, 9...Voltage controlled variable oscillator.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部より供給される入力信号を微分する微分回路と、ク
ロックパルスを発生する電圧制御型可変発振器と、前記
微分回路の正極微分出力の立下り部分にスロープを付与
するスロープ形成回路と、前記スロープ形成回路の出力
を前記クロックパルスの発生に同期してラッチする第1
ラッチ回路と、前記微分回路の微分出力に直流バイアス
を加えて正極性とした信号を前記クロックパルスの発生
に同期してラッチし、その反転出力を送出する第2ラッ
チ回路と、前記第1、第2ラッチ回路の出力レベル差を
求める差動回路と、前記差動回路の出力を平均化して前
記電圧制御型可変発振器に制御信号として供給するロー
パスフィルタとを備え、前記電圧制御型可変発振器から
前記入力信号に応答したクロックパルスを得ることを特
徴とするクロックパルス発生回路。
a differentiating circuit that differentiates an input signal supplied from the outside; a voltage-controlled variable oscillator that generates a clock pulse; a slope forming circuit that imparts a slope to a falling portion of a positive differential output of the differentiating circuit; and the slope forming circuit. a first latching circuit output in synchronization with the generation of the clock pulse;
a latch circuit; a second latch circuit that latches a positive polarity signal by applying a DC bias to the differentiated output of the differentiating circuit in synchronization with the generation of the clock pulse, and sends out an inverted output thereof; a differential circuit for determining the output level difference of the second latch circuit; and a low-pass filter that averages the output of the differential circuit and supplies it as a control signal to the voltage-controlled variable oscillator. A clock pulse generation circuit characterized in that it obtains a clock pulse in response to the input signal.
JP19760281U 1981-12-28 1981-12-28 Clock pulse generation circuit Granted JPS58101314U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19760281U JPS58101314U (en) 1981-12-28 1981-12-28 Clock pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19760281U JPS58101314U (en) 1981-12-28 1981-12-28 Clock pulse generation circuit

Publications (2)

Publication Number Publication Date
JPS58101314U true JPS58101314U (en) 1983-07-09
JPH0317481Y2 JPH0317481Y2 (en) 1991-04-12

Family

ID=30110815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19760281U Granted JPS58101314U (en) 1981-12-28 1981-12-28 Clock pulse generation circuit

Country Status (1)

Country Link
JP (1) JPS58101314U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5184559A (en) * 1975-01-22 1976-07-23 Kokusai Electric Co Ltd
JPS5489259U (en) * 1977-12-07 1979-06-23

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5184559A (en) * 1975-01-22 1976-07-23 Kokusai Electric Co Ltd
JPS5489259U (en) * 1977-12-07 1979-06-23

Also Published As

Publication number Publication date
JPH0317481Y2 (en) 1991-04-12

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