JPS58101247U - analog data input device - Google Patents
analog data input deviceInfo
- Publication number
- JPS58101247U JPS58101247U JP19795281U JP19795281U JPS58101247U JP S58101247 U JPS58101247 U JP S58101247U JP 19795281 U JP19795281 U JP 19795281U JP 19795281 U JP19795281 U JP 19795281U JP S58101247 U JPS58101247 U JP S58101247U
- Authority
- JP
- Japan
- Prior art keywords
- code
- output
- signal
- input device
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例を示す回路ブロック図、第２図
は第１図のＰ−ＲＯＭの出力ビットとゲート群９等の関
係を示す説明図、第３図は上記実施の作用を示すタイミ
ングチャートである。
２・・・・・・Ａ−Ｄ変換器、３・・・・・・カウンタ
、６・・・・・・Ｐ−ＲＯＭ、７・・・・・・アドレス
線、８・・・・・・データ出力用ラッチ。
土
一一］
４１１りＧｙノ
０FIG. 1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the relationship between the output bits of the P-ROM shown in FIG. 1 and the gate group 9, etc., and FIG. FIG. 2...A-D converter, 3...Counter, 6...P-ROM, 7...Address line, 8... Latch for data output. Doichi] 411riGyno0
Claims (1)
基本クロック信号を計数するプログラム制御用カウンタ
と、純２進コードを他の異るコードに変換するためのコ
ード変換情報とシーケンスを指示するシーケンス指令情
報に従い１桁づつ出力するデータ出力用ラッチと、上記
Ａ−Ｄ変換器の出力と上記カウンタの出力を上記基本ク
ロック信号に従い上記Ｐ−ＲＯＭのアドレス線へ交互に
導入する交互切換え手段とを有し、上記アナログ信号を
上記具るコードのデジタル信号によ一リ１桁づつ直列に
出力するよう構成されたアナログデータ入力装置。an A/D converter that converts an analog input signal to digital;
A program control counter that counts basic clock signals, a data output latch that outputs one digit at a time according to code conversion information and sequence command information that instructs a sequence to convert a pure binary code to another different code; an alternating switching means for alternately introducing the output of the A-D converter and the output of the counter to the address line of the P-ROM in accordance with the basic clock signal, and converts the analog signal into a digital signal of the code comprising the code. An analog data input device configured to serially output one digit at a time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19795281U JPS6012181Y2 (en) | 1981-12-25 | 1981-12-25 | analog data input device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19795281U JPS6012181Y2 (en) | 1981-12-25 | 1981-12-25 | analog data input device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58101247U true JPS58101247U (en) | 1983-07-09 |
| JPS6012181Y2 JPS6012181Y2 (en) | 1985-04-20 |
Family
ID=30111155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19795281U Expired JPS6012181Y2 (en) | 1981-12-25 | 1981-12-25 | analog data input device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6012181Y2 (en) |
-
1981
- 1981-12-25 JP JP19795281U patent/JPS6012181Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6012181Y2 (en) | 1985-04-20 |
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