JPS58101230U - Random access memory data protection circuit - Google Patents
Random access memory data protection circuitInfo
- Publication number
- JPS58101230U JPS58101230U JP19536881U JP19536881U JPS58101230U JP S58101230 U JPS58101230 U JP S58101230U JP 19536881 U JP19536881 U JP 19536881U JP 19536881 U JP19536881 U JP 19536881U JP S58101230 U JPS58101230 U JP S58101230U
- Authority
- JP
- Japan
- Prior art keywords
- random access
- access memory
- power source
- protection circuit
- data protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Stand-By Power Supply Arrangements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図及び第3図は、従来のRAMのデータ保護回路の
一例の構成を示す図、第2図は、第1図の回路の1次電
源遮断の瞬間の各接続点の電位波形図、第4図は、本考
案の一実施例の構成を示す図である。
1・・・スピードアップコンデンサ、2. 3. 5゜
8.40,41.42・・・抵抗、4・・・ダイオード
、6.7・・・トランジスタ、9・・・RAM、 10
. 12・・・ダイオード、11・・・2次電源。1 and 3 are diagrams showing the configuration of an example of a conventional RAM data protection circuit, and FIG. 2 is a potential waveform diagram of each connection point of the circuit shown in FIG. 1 at the moment when the primary power supply is cut off. FIG. 4 is a diagram showing the configuration of an embodiment of the present invention. 1...Speed-up capacitor, 2. 3. 5゜8.40, 41.42...Resistor, 4...Diode, 6.7...Transistor, 9...RAM, 10
.. 12...Diode, 11...Secondary power supply.
Claims (1)
電源により常に電力が供給され、記憶情報を保持するラ
ンダム・アクセス・メモリにおいて、前記1次電源接続
時には記憶情報の読出し、書込みを行うための制御信号
を与える回路の最終段を2段の反転器で構成し、前記1
次電源の立ち上がり、立ち下がり時に前記2段の反転器
のうち後段への入力レベルが前段への入力レベルより早
く低レベルになる特性を有するランダム・アクセス・メ
モリのデータ保護回路。When the primary power source obtained from a commercial power source is cut off, power is always supplied from a secondary power source such as a battery, and in a random access memory that retains stored information, when the primary power source is connected, stored information is read and written. The final stage of the circuit that provides the control signal for
A data protection circuit for a random access memory having a characteristic that the input level to the latter stage of the two-stage inverter becomes lower level earlier than the input level to the previous stage when the next power supply rises and falls.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19536881U JPS58101230U (en) | 1981-12-26 | 1981-12-26 | Random access memory data protection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19536881U JPS58101230U (en) | 1981-12-26 | 1981-12-26 | Random access memory data protection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58101230U true JPS58101230U (en) | 1983-07-09 |
JPS6225797Y2 JPS6225797Y2 (en) | 1987-07-01 |
Family
ID=30108646
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19536881U Granted JPS58101230U (en) | 1981-12-26 | 1981-12-26 | Random access memory data protection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58101230U (en) |
-
1981
- 1981-12-26 JP JP19536881U patent/JPS58101230U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6225797Y2 (en) | 1987-07-01 |
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