JPS5797150A - Instruction processing system - Google Patents
Instruction processing systemInfo
- Publication number
- JPS5797150A JPS5797150A JP55173459A JP17345980A JPS5797150A JP S5797150 A JPS5797150 A JP S5797150A JP 55173459 A JP55173459 A JP 55173459A JP 17345980 A JP17345980 A JP 17345980A JP S5797150 A JPS5797150 A JP S5797150A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- accordance
- control
- register
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Retry When Errors Occur (AREA)
Abstract
PURPOSE:To shorten a shifting time from generation of an error to start of restart execution, by a simple configuration, by accessing a control memory in accordance with a result of parity check of plural local memories, and reading out and controlling the corresponding control program. CONSTITUTION:This system is provided with a control memory 4, plural local memories 2 storing the same data, respectively, and the respective parity checking circuits 9, and in accordance with whether a read-out data of each memory 2 is correct or not, an available pattern of all the memories 2 is changed and the instruction is reexecuted. In this case, an address corresponding to the memory 4 is inputted to a register 4, also a controlling program corresponding to an availabe pattern of the memory 2 is stored in the memory 4 in advance so that an address to be set to the register 4 is controlled in accordance with an output of the circuit 9, the control memory 4 is accessed in accordance with a check result of the circuit 9, a corresponding control program is read out, by which the control is executed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55173459A JPS6059610B2 (en) | 1980-12-09 | 1980-12-09 | Instruction processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55173459A JPS6059610B2 (en) | 1980-12-09 | 1980-12-09 | Instruction processing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5797150A true JPS5797150A (en) | 1982-06-16 |
JPS6059610B2 JPS6059610B2 (en) | 1985-12-26 |
Family
ID=15960859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55173459A Expired JPS6059610B2 (en) | 1980-12-09 | 1980-12-09 | Instruction processing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6059610B2 (en) |
-
1980
- 1980-12-09 JP JP55173459A patent/JPS6059610B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6059610B2 (en) | 1985-12-26 |
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