JPS5793455A - Backup system for operating device - Google Patents
Backup system for operating deviceInfo
- Publication number
- JPS5793455A JPS5793455A JP55169241A JP16924180A JPS5793455A JP S5793455 A JPS5793455 A JP S5793455A JP 55169241 A JP55169241 A JP 55169241A JP 16924180 A JP16924180 A JP 16924180A JP S5793455 A JPS5793455 A JP S5793455A
- Authority
- JP
- Japan
- Prior art keywords
- error
- signals
- bus
- memory
- cpu2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
Abstract
PURPOSE:To cooperate backup of multi-stages easily and economically, by locating each central processor on a common bus and determining if the connection to the bus is effective with signals among the processors. CONSTITUTION:At initial condition, assuming that CPUs 1, 2 and 9 have no error, then signals 10, 20 and 90 are all at low state, and a bus effective signal is at high level only for 17, and the signals 27 and 97 are both at low level. Thus, the CPU1 is connected to a memory 3 and an I/O4. The CPU1 is disconnected, if it is in error, and the CPU2 is connected to the memory 3 and the I/O4. Similarly, when the CPU2 also is in error, the CPU9 is connected to the memory section 3 and the I/O4 and the CPUs 1 and 2 are disconnected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55169241A JPS5793455A (en) | 1980-11-28 | 1980-11-28 | Backup system for operating device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55169241A JPS5793455A (en) | 1980-11-28 | 1980-11-28 | Backup system for operating device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5793455A true JPS5793455A (en) | 1982-06-10 |
JPS6131492B2 JPS6131492B2 (en) | 1986-07-21 |
Family
ID=15882852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55169241A Granted JPS5793455A (en) | 1980-11-28 | 1980-11-28 | Backup system for operating device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5793455A (en) |
-
1980
- 1980-11-28 JP JP55169241A patent/JPS5793455A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6131492B2 (en) | 1986-07-21 |
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