JPS5790764A - Method and apparatus for controlling operational sequence of data processor - Google Patents

Method and apparatus for controlling operational sequence of data processor

Info

Publication number
JPS5790764A
JPS5790764A JP56156054A JP15605481A JPS5790764A JP S5790764 A JPS5790764 A JP S5790764A JP 56156054 A JP56156054 A JP 56156054A JP 15605481 A JP15605481 A JP 15605481A JP S5790764 A JPS5790764 A JP S5790764A
Authority
JP
Japan
Prior art keywords
pulse generator
clock pulse
data processor
controlling
operational sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56156054A
Other languages
English (en)
Other versions
JPS6013493B2 (ja
Inventor
Shiyutatsutorumaiyaa Hansu
Shiyutouruchinsuki Warudemaaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Schuckertwerke AG
Siemens AG
Original Assignee
Siemens Schuckertwerke AG
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Schuckertwerke AG, Siemens AG filed Critical Siemens Schuckertwerke AG
Publication of JPS5790764A publication Critical patent/JPS5790764A/ja
Publication of JPS6013493B2 publication Critical patent/JPS6013493B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Retry When Errors Occur (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Debugging And Monitoring (AREA)
JP56156054A 1980-09-30 1981-09-30 デ−タ処理装置の動作シ−ケンスの制御方法および装置 Expired JPS6013493B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3036926.7 1980-09-30
DE3036926A DE3036926C2 (de) 1980-09-30 1980-09-30 Verfahren und Anordnung zur Steuerung des Arbeitsablaufes in Datenverarbeitungsanlagen mit Mikroprogrammsteuerung

Publications (2)

Publication Number Publication Date
JPS5790764A true JPS5790764A (en) 1982-06-05
JPS6013493B2 JPS6013493B2 (ja) 1985-04-08

Family

ID=6113241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56156054A Expired JPS6013493B2 (ja) 1980-09-30 1981-09-30 デ−タ処理装置の動作シ−ケンスの制御方法および装置

Country Status (5)

Country Link
US (1) US4653018A (ja)
EP (1) EP0048991B1 (ja)
JP (1) JPS6013493B2 (ja)
AT (1) ATE7742T1 (ja)
DE (1) DE3036926C2 (ja)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59116858A (ja) * 1982-12-23 1984-07-05 Fujitsu Ltd マシンチエツク割込み処理方式
JPS62204345A (ja) * 1986-03-05 1987-09-09 Oki Electric Ind Co Ltd マイクロコンピユ−タ
US4862352A (en) * 1987-09-16 1989-08-29 Motorola, Inc. Data processor having pulse width encoded status output signal
US5428754A (en) * 1988-03-23 1995-06-27 3Dlabs Ltd Computer system with clock shared between processors executing separate instruction streams
US5325520A (en) * 1992-01-03 1994-06-28 Amdahl Corporation Invoking hardware recovery actions via action latches
US6343363B1 (en) * 1994-09-22 2002-01-29 National Semiconductor Corporation Method of invoking a low power mode in a computer system using a halt instruction
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
JP3323045B2 (ja) * 1995-11-20 2002-09-09 東芝マイクロエレクトロニクス株式会社 情報処理装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3548178A (en) * 1968-01-18 1970-12-15 Ibm Computer error anticipator
US3593297A (en) * 1970-02-12 1971-07-13 Ibm Diagnostic system for trapping circuitry
US3651475A (en) * 1970-04-16 1972-03-21 Ibm Address modification by main/control store boundary register in a microprogrammed processor
US3656123A (en) * 1970-04-16 1972-04-11 Ibm Microprogrammed processor with variable basic machine cycle lengths
US3764992A (en) * 1972-02-14 1973-10-09 Bell Telephone Labor Inc Program-variable clock pulse generator
NL7207216A (ja) * 1972-05-27 1973-11-29
US3784801A (en) * 1972-07-12 1974-01-08 Gte Automatic Electric Lab Inc Data handling system error and fault detecting and discriminating maintenance arrangement
DE2237925B2 (de) * 1972-08-02 1975-11-27 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zur Fehleranalyse und zur Fehlerbeseitigung in elektronischen Datenverarbeitungssystemen unter Einsatz eines Dienstrechners
DE2248451C3 (de) * 1972-10-03 1979-11-22 Ibm Deutschland Gmbh, 7000 Stuttgart Prüfverfahren und Schaltungsanordnung in Datenverarbeitungsanlagen
FR2269148B1 (ja) * 1974-04-25 1978-01-20 Honeywell Bull Soc Ind
IT1046598B (it) * 1974-05-16 1980-07-31 Honeywell Inf Systems Interfaccia di connessione di apparecchiature periferiche a un calcolatore provvista di meccanismi di segnalazione e di distinzione tradiversi tipi di errore
US4057847A (en) * 1976-06-14 1977-11-08 Sperry Rand Corporation Remote controlled test interface unit
DE2737133C2 (de) * 1977-08-17 1979-07-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zum Verhindern von Doppelfehlern in einer Datenverarbeitungsanlage
US4130240A (en) * 1977-08-31 1978-12-19 International Business Machines Corporation Dynamic error location

Also Published As

Publication number Publication date
ATE7742T1 (de) 1984-06-15
DE3036926A1 (de) 1982-04-15
EP0048991B1 (de) 1984-05-30
US4653018A (en) 1987-03-24
JPS6013493B2 (ja) 1985-04-08
EP0048991A1 (de) 1982-04-07
DE3036926C2 (de) 1984-07-26

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