JPS5789362A - Automatic adjusting circuit for discrimination level - Google Patents

Automatic adjusting circuit for discrimination level

Info

Publication number
JPS5789362A
JPS5789362A JP16615580A JP16615580A JPS5789362A JP S5789362 A JPS5789362 A JP S5789362A JP 16615580 A JP16615580 A JP 16615580A JP 16615580 A JP16615580 A JP 16615580A JP S5789362 A JPS5789362 A JP S5789362A
Authority
JP
Japan
Prior art keywords
levels
level
discrimination
comparators
detect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16615580A
Other languages
Japanese (ja)
Inventor
Eisuke Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16615580A priority Critical patent/JPS5789362A/en
Publication of JPS5789362A publication Critical patent/JPS5789362A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To prevent the degradation of the discrimination error rate due to the distortion and the level fluctuation of a receiving signal, by using maximum and minimum levels of a multilevel signal as new discrimination levels to detect the level of the receiving signal and controlling plural discrimination levels. CONSTITUTION:The quad pulse train from a transmission line is inputted to comparators D1-D3 and is compared with discrimination levels T1-T3 and is outputted as two-bit parallel binary pulse trains from output terminals 5-1, and 5-2. Meanwhile, comparators A1 and A2 compare signals of level 0 and level 3 in the quad pulse train of levels 0-3 with discrimination levels TA1 and TA2 to detect an outside or inside distortion of the actual eye pattern for an ideal eye pattern. These detection outputs a1, a2, d1, and d2 are used to set an output Y of an OR gate G2 to ''1'' or ''0''.
JP16615580A 1980-11-26 1980-11-26 Automatic adjusting circuit for discrimination level Pending JPS5789362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16615580A JPS5789362A (en) 1980-11-26 1980-11-26 Automatic adjusting circuit for discrimination level

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16615580A JPS5789362A (en) 1980-11-26 1980-11-26 Automatic adjusting circuit for discrimination level

Publications (1)

Publication Number Publication Date
JPS5789362A true JPS5789362A (en) 1982-06-03

Family

ID=15826078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16615580A Pending JPS5789362A (en) 1980-11-26 1980-11-26 Automatic adjusting circuit for discrimination level

Country Status (1)

Country Link
JP (1) JPS5789362A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60174550A (en) * 1984-02-21 1985-09-07 Nippon Telegr & Teleph Corp <Ntt> Code regenerating circuit
JPS61123671A (en) * 1984-09-26 1986-06-11 チバ−ガイギ　アクチエンゲゼルシヤフト Reactive dye, its production and use
EP0330177A2 (en) * 1988-02-22 1989-08-30 Fujitsu Limited Circuit for generating discrimination level voltage

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60174550A (en) * 1984-02-21 1985-09-07 Nippon Telegr & Teleph Corp <Ntt> Code regenerating circuit
JPS61123671A (en) * 1984-09-26 1986-06-11 チバ−ガイギ　アクチエンゲゼルシヤフト Reactive dye, its production and use
EP0330177A2 (en) * 1988-02-22 1989-08-30 Fujitsu Limited Circuit for generating discrimination level voltage
US5001726A (en) * 1988-02-22 1991-03-19 Fujitsu Limited Circuit for generating discrimination voltage level

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