JPS5750128A - Signal binary coding device - Google Patents
Signal binary coding deviceInfo
- Publication number
- JPS5750128A JPS5750128A JP12453180A JP12453180A JPS5750128A JP S5750128 A JPS5750128 A JP S5750128A JP 12453180 A JP12453180 A JP 12453180A JP 12453180 A JP12453180 A JP 12453180A JP S5750128 A JPS5750128 A JP S5750128A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- threshold value
- binary
- signals
- binary coding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To achieve accurate binary coding without distorting waveform by producing a delay signal the same shape as an input signal, setting the threshold value through floating this signal, and outputting a signal of 1 or 0 level depending on whether the input signal is lower or higher than the threshold value. CONSTITUTION:A video signal obtained from a photomask with an image sensor 21 of a signal binary coding device is respectively inputted to comparators 23, 24, it is compared with a high threshold value 13 set at a power supply 25 through the comparator 23 and compared with a low threshold value 14 set by a power supply 26 at the comparator 24. The video signal is binary-coded at the comparators 23, 24, and binary-conded outputs 15 and 16 are outputted to the high and low threshold values 13 and 14, and logical calculation is made at a logical circuit such as an AND gate. A signal 17 rejecting signals 15, 16 corresponding to white and black point signals 19, 20 is stored in an FF34 and an output F at 1 is outputted. The logic between signals 17, and 15, 16 is taken at the logic circuit to output binary signal 18 corresponding to white and black patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12453180A JPS5750128A (en) | 1980-09-10 | 1980-09-10 | Signal binary coding device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12453180A JPS5750128A (en) | 1980-09-10 | 1980-09-10 | Signal binary coding device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5750128A true JPS5750128A (en) | 1982-03-24 |
Family
ID=14887774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12453180A Pending JPS5750128A (en) | 1980-09-10 | 1980-09-10 | Signal binary coding device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5750128A (en) |
-
1980
- 1980-09-10 JP JP12453180A patent/JPS5750128A/en active Pending
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