JPS5787265A - Reproducing circuit for receiving data - Google Patents
Reproducing circuit for receiving dataInfo
- Publication number
- JPS5787265A JPS5787265A JP16139380A JP16139380A JPS5787265A JP S5787265 A JPS5787265 A JP S5787265A JP 16139380 A JP16139380 A JP 16139380A JP 16139380 A JP16139380 A JP 16139380A JP S5787265 A JPS5787265 A JP S5787265A
- Authority
- JP
- Japan
- Prior art keywords
- counter
- count
- counters
- difference
- count value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To reproduce data in a high-reliability state, by controlling sampling colcks so that the count value of the second counter has a prescribed difference for the count value of the first counter. CONSTITUTION:The count value of a counter 22 is used as a write address to store inputted receiving data DIN in a buffer register 21 successively, and stored data read out successively by a count signal C2 of a counter 23 and are outputted as reproduced signal DOUT. Counters 22 and 23 have the same count quantity, and a difference N/2 is held between count contents of both counters. A phase locked loop is constituted by a comparator 24, a voltage control oscillator 25, and the counter 23 to perform such control that the differential phase between carrier-up signals CU1 and CU2 outputted from counters 22 and 23 is always 90 deg., thus holding the difference between count contents of counters in N/2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16139380A JPS5787265A (en) | 1980-11-18 | 1980-11-18 | Reproducing circuit for receiving data |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16139380A JPS5787265A (en) | 1980-11-18 | 1980-11-18 | Reproducing circuit for receiving data |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5787265A true JPS5787265A (en) | 1982-05-31 |
Family
ID=15734232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16139380A Pending JPS5787265A (en) | 1980-11-18 | 1980-11-18 | Reproducing circuit for receiving data |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5787265A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0536464A2 (en) * | 1991-10-10 | 1993-04-14 | Nec Corporation | SONET DS-N desynchronizer |
-
1980
- 1980-11-18 JP JP16139380A patent/JPS5787265A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0536464A2 (en) * | 1991-10-10 | 1993-04-14 | Nec Corporation | SONET DS-N desynchronizer |
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