JPS5787252A - Compensating system for step out of pcm signal - Google Patents

Compensating system for step out of pcm signal

Info

Publication number
JPS5787252A
JPS5787252A JP55162366A JP16236680A JPS5787252A JP S5787252 A JPS5787252 A JP S5787252A JP 55162366 A JP55162366 A JP 55162366A JP 16236680 A JP16236680 A JP 16236680A JP S5787252 A JPS5787252 A JP S5787252A
Authority
JP
Japan
Prior art keywords
data
signal
synchronizing signals
detected
clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55162366A
Other languages
Japanese (ja)
Other versions
JPS6253097B2 (en
Inventor
Tatsukoshi Shinohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Aerojet Rocketdyne Holdings Inc
Original Assignee
Fujitsu General Ltd
Gencorp Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd, Gencorp Inc filed Critical Fujitsu General Ltd
Priority to JP55162366A priority Critical patent/JPS5787252A/en
Publication of JPS5787252A publication Critical patent/JPS5787252A/en
Publication of JPS6253097B2 publication Critical patent/JPS6253097B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

PURPOSE:To keep intervals of synchronizing signals in a data signal normal, by increasing or decreasing the number of clocks by the number of bits for the step-out of data at the time of the least data loss in case that the step-out of synchronization is detected during reproducing of a PCM signal. CONSTITUTION:Synchronizing signals are detected from a disc reproduced signal, and the irregularity of intervals of detected synchronizing signals is detected, and data is written to a storage element 21 by a clock signal phi1' where the number of clocks is increased or decreased by the number of bits for the step- out of data at the time of the least data loss on a basis of the detection signal, and data is read out by a clock signal phi2, which is not subjected to this adjustment for the number of clocks, to compensate the step-out of synchronization. Thus, intervals of synchronizing signals in the data signal are kept in a normal state.
JP55162366A 1980-11-18 1980-11-18 Compensating system for step out of pcm signal Granted JPS5787252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55162366A JPS5787252A (en) 1980-11-18 1980-11-18 Compensating system for step out of pcm signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55162366A JPS5787252A (en) 1980-11-18 1980-11-18 Compensating system for step out of pcm signal

Publications (2)

Publication Number Publication Date
JPS5787252A true JPS5787252A (en) 1982-05-31
JPS6253097B2 JPS6253097B2 (en) 1987-11-09

Family

ID=15753191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55162366A Granted JPS5787252A (en) 1980-11-18 1980-11-18 Compensating system for step out of pcm signal

Country Status (1)

Country Link
JP (1) JPS5787252A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5967746A (en) * 1982-10-12 1984-04-17 Fujitsu Ltd Circuit for detecting multi-point monitoring frame synchronizing pattern
JPS6128246A (en) * 1984-07-18 1986-02-07 Nec Corp Reception time axis renewing circuit of time division multiple access device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5967746A (en) * 1982-10-12 1984-04-17 Fujitsu Ltd Circuit for detecting multi-point monitoring frame synchronizing pattern
JPH0134491B2 (en) * 1982-10-12 1989-07-19 Fujitsu Ltd
JPS6128246A (en) * 1984-07-18 1986-02-07 Nec Corp Reception time axis renewing circuit of time division multiple access device
JPH0525208B2 (en) * 1984-07-18 1993-04-12 Nippon Electric Co

Also Published As

Publication number Publication date
JPS6253097B2 (en) 1987-11-09

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