JPH0525208B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time division multiple access device used in satellite communications and the like. In particular, a frame synchronization code is detected from the received data string that makes up the frame, and the time indicated by this detection timing is used to detect the received frame period, and a common received frame time width is determined between each station. The present invention relates to a reception time axis update circuit of a time division multiple access device that determines and establishes.

[Conventional technology]

In the time division multiple access (hereinafter referred to as "TDMA") satellite communication system, each earth station accessing the satellite transmits its own signal so that the data signals transmitted by other stations on the satellite repeater do not overlap in time. A communication line between multiple stations is established by transmitting data in synchronization with a reference burst. That is, the data signal emitted from each station is in the form of a burst, and this burst-like data is sent to a burst position designated for each station at a predefined period (frame period).

In order to receive and process burst-like data arranged in this way, in the conventional method, a burst-like data is emitted once every n frames (n is a positive integer) from one or more reference stations of each station participating in TDMA. Detects the frame synchronization code in the data, resets the receive frame counter that determines the receive frame time axis within each station based on this detection timing, determines the receive frame time axis common to each station, and uses this determined one frame. Using various timings generated at fixed bit positions from the position of the inter-axis axis in was being processed.

FIG. 3 is a block diagram of a conventional circuit. In FIG. 3, a frame synchronization code detection timing signal a is inputted from a device that extracts a frame synchronization code from a received data string having a frame structure, and at the timing of this signal, the reception time axis information generation circuit 14 generates a received frame. The counter circuit is reset, the reception time axis information f is outputted, and the reception frame time axis is determined. This reception time axis information f is
It is used to generate various timing signals and control signals for processing the received data that makes up the frame.

Therefore, if the insertion position of the frame synchronization code is specified at a frame break, the conventional circuit for determining the received frame time axis shown in FIG. 3 is sufficient and there is no particular problem.

[Problem that the invention seeks to solve]

However, the insertion position of the frame synchronization code, that is, the frame counter and reset timing that define the received frame time axis within each station do not necessarily exist at frame breaks.

In Intelsat's TDMA system, if a failure occurs in the reference station, there is a method in which the burst of the reference station backup station is controlled as the reference burst (the system used on the Intelsat ship, the reference is Intelsat). Specifications for Intel 196 1981).

In this case, the frame synchronization code from the reference station backup station appears at the burst position of that station, so it appears not at the beginning of the frame but in the middle. In such a case, if the receive frame counter is reset at the timing of receiving the frame synchronization code from the reference station backup station, it will be reset to the time period in which received burst data exists, and various timing signals and various controls will be reset. There is a problem that distortion occurs in the signal and the received data cannot be processed normally. For example, the reception frame counter is reset at the rising edge of the internal clock, causing distortion in various timing signals and control signals necessary for processing reception data at the station.

In particular, when there is a relative position error between the predicted reception position of the frame synchronization code in the received frame and the reception position of the frame synchronization code, such as when reception time fluctuations exist due to satellite position fluctuations. When the frame synchronization code is received at a time position where burst processing is being performed at the time when received burst-like data exists and the receive frame counter circuit is reset, the necessary data part is extracted from the received burst-like data. There were serious problems such as distortions occurring in various timing signals and various control signals required for processing, and the received data could not be processed normally.

The present invention has been made by focusing on such conventional problems, and by resetting the received frame counter in an area where no received burst-like data exists, regardless of the insertion position of the frame synchronization code, It is an object of the present invention to provide a reception time axis update circuit that sets the time axis of a reception frame that enables normal processing of received burst data.

[Means for solving problems]

According to the present invention, even if an error occurs in the receiving position of the frame synchronization code, various timing signals and control signals used for processing the received burst data are not present, that is, in an area where distortion does not occur in the processing of the received burst data. The present invention is characterized by comprising a device capable of updating a received frame time axis.

That is, there is a means for extracting a frame synchronization code from a frame-configured received data string, and a means for updating a receive frame counter that determines the time axis of a received frame based on the detection timing of this frame synchronization code to obtain time axis information of the received frame. In a reception time axis update circuit of a time division multiple access device, the reception time axis information generation circuit outputs a reception time axis information generating circuit, and determines the time axis of a reception frame common to each station in a time division multiple access system. The relative position error between the detected position and the predicted detected position is calculated from the detected position of the frame synchronization code, the frame synchronization code insertion position information signal, and the predicted detection position of this frame synchronization code set in advance. A means for measuring at the timing of inputting a timing signal and outputting detected position error information according to the relative position error; and a means for inputting the timing signal and delaying the timing signal by an amount specified by the detected position error information. The signal output from the variable delay circuit is input to the reception time axis information generation circuit, and the reception time axis information generation circuit generates the time indicated by the output signal of the variable delay circuit. A circuit that generates reception time axis information that specifies a new reception frame time axis after being reset to The apparatus is characterized in that it includes a circuit that generates the timing signal at a time preceding the end of the frame.

The means for outputting the detected position error information includes a reception position information temporary storage circuit which inputs the frame synchronization code detection timing signal and the frame synchronization code insertion position information and outputs the frame synchronization code reception position information; It is preferable to include a frame synchronization code position error detection circuit that inputs the predicted detection position of the synchronization code reception position information and determines the amount of variation in the reception position of the frame synchronization code based on the timing of the timing signal.

Further, the means for outputting the detected position error information measures the relative error between the detected position of the frame synchronization code inputted from the extraction means and the detected position of this frame synchronization code set in advance, and It can also be configured to output detected position error information according to the error.

[Effect]

The present invention detects a frame synchronization code from a received data string constituting a frame, and uses the time indicated by this detection timing to establish a received frame time axis common to each station. The reception frame counter that counts the number of bursts is reset at the end position of the reception frame where there is no burst data.

In particular, when the reference station is backed up and the backup reference burst is not at the beginning of the received frame, the reset timing of the received frame counter is set to the end position of the received frame without received burst-like data, and various timing signals in the ground station are distorted. prevent this from occurring.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram illustrating a first embodiment of the present invention. In this embodiment, one frame is m
bits (m is an integer of 2 or more), and the relative positional error between the frame synchronization code detection position and this detected predicted position is a maximum of A bits, and this relative positional error A is 2A+1≦m (A is positive This is the case when the following relationship is satisfied (an integer of

In FIG. 1, frame synchronization code detection timing signal a and frame synchronization code insertion position information b indicating the bit position where the frame synchronization code is inserted (signal indicating the bit position where the frame synchronization code is inserted) ) is output from a receiving device that extracts a frame synchronization code from a received data string having a frame structure, and is input to a frame synchronization code detection position error measurement circuit 10. This frame synchronization code detection position error measurement circuit 10 is as follows:
Reception position information temporary storage circuit 11 which is an m-bit cycle counter that inputs the above two signals and information.
and a frame synchronization code position error detection circuit 12 which receives frame synchronization code reception position information c to be output from now. The frame synchronization code position error detection circuit 12 outputs detected position error information d that determines the relative position error between the frame synchronization code detection position and this detected predicted position, that is, the amount of variation in the frame synchronization code reception position.
The signal is output to the variable delay circuit 13. The received time axis update timing signal e from this variable delay circuit 13 is
The signal is output to the reception time axis information generation circuit 14, which includes a reception frame counter and the like. The reception time axis information generation circuit 14 outputs reception time axis information f used for reception data processing, and further indicates A bit before the end position of the reception frame indicating the predicted detection position of the frame synchronization code. A timing signal g is output to the frame synchronization code position error detection circuit 12 and the variable delay circuit 13.

The reception position information temporary storage circuit 11 writes the value indicated by the frame synchronization code insertion position information b as the initial value of the counter according to the timing of the frame synchronization code detection timing signal a, and then writes m bits as one period. By repeating the count, the detection position information of the frame synchronization code detection timing signal a is held until the next frame synchronization code detection timing, and the frame synchronization code reception position information is sent to the frame synchronization code position error detection circuit 12. Output c.

The frame synchronization code position error detection circuit 12 detects a frame synchronization code that is repeated at an m-bit period, including relative position error information between a frame synchronization code detection position and a preset predicted detection position of this code. The reception position information c is sampled at a position indicated by a timing signal g that is ahead of the reception detection position of the frame synchronization code by the maximum possible relative position error A bit with respect to the predicted detection position. From this sampling result, a relative position error of X bits is detected,
Also, from this relative position error X bits, the distance to the end of the frame is determined by (A+1)-X,
This distance is output to the variable delay circuit 13 as detected position error information d.

The variable delay circuit 13 has a maximum delay amount of 2A+1 bits, receives the detected position error information d and the timing signal g output from the frame synchronization code position error detection circuit 12, and receives the detected position error information d.
A delay of an amount indicated by is given to the timing signal g, and outputted to the reception time axis information generation circuit 14 as a reception time axis update timing signal e.

The reception time axis information generation circuit 14 determines and outputs the reception time axis information f by resetting at the timing of the reception time axis update timing signal e indicating the end of the frame.

In this way, the frame synchronization code detection timing signal a is
If bits (X is a positive integer) are received in advance, the frame synchronization code position error detection circuit 12
The detected position error information d output from indicates the value of A + 1 - The information d indicates the value of A+1-Y and is sent to the variable delay circuit 13.

With this configuration, by sampling the counter value at the timing of the timing signal given by the maximum relative error A, the relative position error X or Y bits can be found.

The variable delay circuit 13 inputs a timing signal g that precedes the frame by A bits from the end of the frame, gives this timing signal g a delay of an amount indicated by the detection position error information d, and changes the position of the frame synchronization code detection timing. A signal indicating the end position of the frame corresponding to the frame is sent to the reception time axis information generation circuit 14 as the reception time axis update timing signal e.

The reception time axis information generation circuit 14 is reset at the position indicated by the reception time axis update timing signal e, that is, at the end position of the frame corresponding to the positional change of the frame synchronization code detection timing, so that it does not interfere with the reception data processing. without giving
It is possible to determine and output received time axis information.

Here, FIG. 4 shows a time chart of this embodiment and will be explained.

Assume that a frame synchronization code is located at the Nth bit within one frame (m bits). Each station detects the frame synchronization code and outputs a frame synchronization code detection timing signal a. The frame synchronization code insertion position information b indicates the Nth bit, and the reception position information temporary storage circuit (m-bit period counter) 11 uses the frame synchronization code insertion position information b as a load signal to insert the frame synchronization code. Outputs received position information c. This frame synchronization code reception position information c may differ from the predicted detected position due to positional fluctuations of the satellite and the asynchronous clock frequencies of the transmitting station and the receiving station. Therefore, the frame synchronization code reception position information c and the detected predicted position are compared at the timing of the timing signal g that is a maximum relative position error A bit before the end position of the frame. In the example shown in FIG. 4, the t-th bit of the frame synchronization code reception position information c is compared with the t-2nd bit of the detected predicted position, and the relative position error is 2 bits. The frame synchronization code position error detection circuit 12 performs these operations and outputs detected position error information d indicating the number of bits up to the beginning position of the next frame. In this FIG. 4, it becomes (A+1)-2. Variable delay circuit 13
is the timing signal g based on the detected position error information d.
is delayed by (A+1)-2 bits and a reception time axis update timing signal e is output. The reception time axis information generation circuit (reception frame counter) 14 is reset by the reception time axis update timing signal e,
Outputs reception time axis information f.

FIG. 2 is a block diagram illustrating a second embodiment of the present invention. In particular, the means for obtaining the detected position error information d is different from the first embodiment. As shown in FIG. 2, the frame synchronization code detection position error measurement circuit 20 receives a frame synchronization code detection timing signal a and frame synchronization code detection predicted position information h. The frame synchronization code detection position error measuring circuit 20 is comprised of a set-reset type flip-flop circuit to which the above two types of signals and information are input, and a counter for counting the width of the output of this flip-flop circuit.

Hereinafter, a variable delay circuit 13 inputs the detected position error information d and timing signal g and outputs a reception time axis update timing signal e, and further inputs the reception time axis update timing signal e, and inputs the reception time axis information f and the variable delay circuit 13. The configuration and operation of the reception time axis information generation circuit 14 that outputs the timing signal g to the delay circuit 13 are the same as those described in the first embodiment.

This embodiment is an embodiment in which a time region in which received data is empty exists at the end position of a frame. However, if there is an area where the received data is empty only in the time area other than the end position of the frame, the received data can be processed by generating the timing A bit before the empty time position as the timing signal g. A circuit that can update and generate received time axis information without causing any trouble can be easily realized.

〔Effect of the invention〕

The present invention provides a circuit that sets and updates the time axis of a received frame common to each ground station of a TDMA device, so that even if the insertion position of the frame synchronization code is not at the beginning of the frame, it does not interfere with the received data processing. Correct received data processing can be performed without giving

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a block diagram showing a second embodiment of the present invention. FIG. 3 is a block diagram illustrating a conventional circuit. FIG. 4 is a time chart explaining the operation of the first embodiment. 10, 20... Frame synchronization code detection position error measurement circuit, 11... Receiving position information temporary storage circuit, 12... Frame synchronization code position error detection circuit, 13... Variable delay circuit, 14... Reception time axis Information generating circuit, a... Frame synchronization code detection timing signal, b... Frame synchronization code insertion position information, c... Frame synchronization code reception position information, d... Detection position error information, e... Reception time Axis update timing signal, f... Reception time axis information, g
. . . Timing signal, h . . . Frame synchronization code detection predicted position information.

Claims (1)

[Scope of Claims] Means for extracting a frame synchronization code from a received data string having a one-frame configuration; In the reception time axis update circuit of a time division multiple access device, which includes a reception time axis information generation circuit that outputs frames and time axis information, and determines the time axis of a reception frame common to each station in a time division multiple access system, From the detected position of the frame synchronization code input from the extraction means, the frame synchronization code insertion position information signal, and the predicted detection position of this frame synchronization code set in advance, the detected position and the predicted detection position are determined. a means for measuring a relative position error at the timing of inputting a timing signal and outputting detected position error information corresponding to the relative position error; and a variable delay circuit that delays this timing signal, the signal output from this variable delay circuit is input to the reception time axis information generation circuit, and this reception time axis information generation circuit outputs the output of the variable delay circuit. A circuit that generates reception time axis information that specifies a new reception frame time axis by being reset to the time indicated by the signal, and a relative position error between the detection position of the frame synchronization code and the predicted detection position. A receiving time axis update circuit for a time division multiple access device, comprising: a circuit for generating the timing signal at a time preceding the end of the frame by a maximum bit amount. 2. The means for outputting the detected position error information is a reception position information temporary storage circuit which inputs the frame synchronization code detection timing signal and the frame synchronization code insertion position information and outputs the frame synchronization code reception position information. and a frame synchronization code position error detection circuit that receives the frame synchronization code reception position information and the predicted detection position and determines the amount of variation in the reception position of the frame synchronization code based on the timing of the timing signal. A reception time axis update circuit for a time division multiple access device according to claim 1. 3. A means for extracting a frame synchronization code from a frame-configured received data string, and a means for extracting a frame synchronization code from a frame-configured received data string, and updating a receive frame counter that determines a received frame time axis based on the detection timing of this frame synchronization code to update time axis information of the received frame. In a reception time axis update circuit of a time division multiple access device, which is equipped with a reception time axis information generation circuit to output, and which determines the time width of a reception frame common to the time division multiple access system and each station, means for measuring a relative position error between a detected position of a frame synchronization code and a preset predicted detection position of the frame synchronization code, and outputting detected position error information according to the relative position error; and a timing signal. and a variable delay circuit that delays the timing signal by an amount specified by the detected position error information, and the signal output from the variable delay circuit is input to the reception time axis information generation circuit, This reception time axis information generation circuit includes a circuit that generates reception time axis information that specifies a new reception frame time axis by being reset to a time indicated by the output signal of the variable delay circuit, and a circuit that detects the frame synchronization code. and a circuit for generating the timing signal at a time preceding the end of the frame by the maximum possible bit of the relative position error between the detected predicted position and the detected predicted position. Time axis update circuit.