JPS6128246A - Reception time axis renewing circuit of time division multiple access device - Google Patents

Abstract

PURPOSE:To renew a reception frame time axis to a region where various timing signals and control signals do not exist by generating reception frame time axis information corresponding to a reception position of a frame synchronizing code. CONSTITUTION:Frame synchronizing code reception position information (c) is outputted to a frame synchronizing code position error detection circuit 12. A variable delay circuit 13 inputs a timing signal (g) preceding by A bits from the end of a frame, gives a delay commanded by detection position error information (d) to the timing signal (g) and a signal indicating the end position of the frame is transmitted to a reception time axis information generating circuit 14 as a reception time axis renewal timing signal (e) to a reception time axis information generating circuit 14. The reception time axis information generating circuit 14 is reset at the end position of the frame corresponding to the position commanded by the reception time axis renewal timing signal (e), that is, the end position of the frame. Thus, the reception time axis information is confirmed and outputted without giving any hindrance to the reception data processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time division multiple access device used in satellite communications and the like. In particular, the reception time axis of a time division multiple access device is updated by detecting a frame synchronization code from the received data string that constitutes a frame and determining the reception frame time axis using the time indicated by this detection timing. Regarding circuits.

[Conventional technology]

In the time division multiple access (hereinafter referred to as rTDMAJ) satellite communication system, each earth station accessing the satellite transmits its own signal so that it does not overlap in time with the data signals transmitted by other stations on the satellite repeater. , a communication line between multiple stations is established by transmitting in synchronization with a reference burst. That is, the data signals emitted from each station are in the form of a burst, and the burst data is sent out at a designated position in a predetermined period (frame period).

In order to receive and process the burst data arranged in this way, in the conventional method, each station participating in TDMA -
Or from multiple reference stations, n frames (n is a positive integer)
The frame synchronization code in the burst data that is emitted once is detected, and the reception frame counter that determines the reception frame time axis within each station is reset based on this detection timing. The axis is determined, and using various timings defined by this determined frame time axis, only the data part necessary for each station is extracted from the received burst data group, and this extracted data is transmitted to each burst flower. It was processed accordingly.

FIG. 3 is a block diagram of a conventional circuit.

In FIG. 3, a frame synchronization code detection timing signal a is inputted from a device that extracts a frame synchronization code from a received data string having a frame structure, and at the timing of this signal, the reception time axis information generation circuit 14 generates a received frame. The counter circuit is reset, the reception time axis information f is outputted, and the reception frame time axis is determined. This reception time axis information f is used to generate various timing signals, control signals, etc. for processing the reception data forming the frame.

Therefore, when the insertion position of the frame synchronization code is specified at a frame break, the conventional circuit for determining the received frame time axis shown in FIG. 3 is sufficient and there is no particular problem.

[Problem that the invention seeks to solve]

However, the insertion position of the frame synchronization code, that is, the reset timing of the frame counter that defines the received frame time axis within each station does not necessarily exist at a frame break. This occurs when the frequency of the clock that sends the frame synchronization code is asynchronous with the clock frequency of the stations participating in this communication line, or when the satellite receives burst data received via this communication line. This can be seen when there are reception time fluctuations due to location fluctuations, etc. In such a case, discontinuities occur on the received frame time axis during the time period in which received burst data exists, so various timing signals and signals required to extract the necessary data part from the received burst data are There were serious problems such as distortion in various control signals and the inability to properly process received data.

That is, in FIG. 3, if there is a relative position error in the frame synchronization code detection timing signal a with respect to the predicted reception position of this signal, the reception frame counter circuit of the reception time axis information generation circuit 14 A discontinuous point occurs in the reception time axis information f at the point in time when it is reset at the timing of the synchronization code detection timing signal a.

If this discontinuity point is in an area where received data exists, there is a problem in that various timing signals and control signals used for processing the received data are distorted, so that the received data cannot be processed normally.

The present invention has been made by focusing on such conventional problems.The present invention extracts a frame synchronization code from a received data string constituting a frame, and performs reception using this frame synchronization code detection timing. When determining the frame time axis, regardless of the insertion position of the frame synchronization code,
It is an object of the present invention to provide a device for determining a received frame time axis that enables normal processing of received burst data.

[Means for solving problems]

According to the present invention, even if an error occurs in the receiving position of the frame synchronization code, various timing signals and control signals used for processing received burst data do not exist, that is, an area where distortion does not occur in processing received burst data. The present invention is characterized by comprising a device capable of updating a received frame time axis.

That is, the time division system is equipped with a means for extracting a frame synchronization code from a received data string having a frame structure, and a reception time axis information generation circuit that sets a reception frame time axis using the detection timing of this frame synchronization code. In the reception time axis update circuit of the multiple access device, the relative position error between the detected position of the frame synchronization code input from the extraction means and the predicted detected position of this code set in advance is measured, and the detected position error information is obtained. and a variable delay circuit for inputting a timing signal and delaying the timing signal by an amount specified by the detected position error information output from the outputting means, and outputting from the variable delay circuit. The received signal is input to a reception time axis information generation circuit, and this reception time axis information generation circuit is reset to the time indicated by the output signal of the variable delay circuit and generates reception time axis information specifying a new reception frame time axis. and a circuit that generates a timing signal at a time preceding the detected position of the frame synchronization code by the maximum possible bit of the relative position error between the detected position and the detected predicted position. do.

The means for outputting the detected position error information includes a reception position information temporary storage circuit which inputs the frame synchronization code detection timing signal and the frame synchronization code insertion position information and outputs the frame synchronization code reception position information; It is preferable to include a frame synchronization code position error detection circuit that inputs synchronization code reception position information and further inputs a timing signal to determine the amount of variation in the reception position of the frame synchronization code.

[Effect]

The present invention detects a frame synchronization code from a received data string constituting a frame, and when determining the received frame time axis using the time indicated by this detection timing, the frame synchronization code is received. By generating received frame time axis information corresponding to the position, it is possible to update the received frame time axis in an area where various timing signals and control signals do not exist.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram illustrating a first embodiment of the present invention. In this embodiment, ■The frame consists of a β channel (j!, m is an integer of 2 or more) consisting of m bits,
The maximum relative position error between the frame synchronization code detection position and this detected predicted position is A bit, and this relative position error A
satisfies the relationship 2A+1≦m (A is a positive integer), and there is a time region at the end of the frame in which received data is empty.

In FIG. 1, the frame synchronization code detection timing signal a and the frame synchronization code insertion position information indicating the position information where the frame synchronization code is inserted are the frame synchronization code detection timing signal a and the frame synchronization code insertion position information indicating the position information where the frame synchronization code is inserted. It is output from the receiving device to be extracted and input to the frame synchronization code detection position error measurement circuit 10. This frame synchronization code detection position error measurement circuit 10 includes a reception position information temporary storage circuit 1) which is an m-bit cycle counter that inputs the above two signals and information, and a frame synchronization code reception position information IIAC that is output from this circuit. and a frame synchronization code position error detection recess 1s12 which receives as input. The frame synchronization code position error detection circuit 12 outputs detected position error information d that determines the relative position W error between the frame synchronization code detection position and this detected predicted position, that is, the amount of variation in the frame synchronization code reception position. , are output to the variable delay circuit 13. The reception time axis update timing signal e is outputted from the variable delay circuit I3 to the reception time axis information generation circuit 14, which includes a reception frame counter and the like. The reception time axis information generation circuit 14 outputs reception time axis information f used for reception data processing, and further indicates A bits before the end position of the reception frame indicating the predicted detection position of the frame synchronization code. A timing signal g is output to the frame synchronization code position error detection circuit I2 and the variable delay circuit 13.

The reception position information temporary storage circuit 1) writes the value already indicated by the frame synchronization code insertion position information as the initial value of the count according to the timing of the frame synchronization code detection timing signal a, and then writes m bits in one cycle. By repeating the count, the detection position information of the frame synchronization code detection timing signal a is held until the next frame synchronization code detection timing, and the frame synchronization code position error detection circuit 12 stores the frame synchronization code reception position information. Output information C.

The frame synchronization code position error detection circuit 12 includes relative position error information between the frame synchronization code detection position and the predicted detection position of this code, which is set in a
Frame synchronization code reception position information C, which is repeated at a bit period, is indicated by a timing signal g that precedes the reception detection position of the frame synchronization code by a bit to the maximum possible relative position error between the frame synchronization code reception detection position and the predicted detection position. sampled at the location where From this sampled result, by determining the distance between the indicated value and the end of the m-bit counter, that is, the end of the frame, the amount of variation in the receiving position of the frame synchronization code is determined, and the detected position error information d
The signal is output to the variable delay circuit 13 as a signal.

The variable delay circuit 13 has a maximum delay amount of 2A+1 pits, receives the detected position error information d and the timing signal g output from the frame synchronization code position error detection circuit 12, and receives the detected position error information @d. The timing signal g is given a delay by an amount equal to the amount of delay, and is output to the reception time axis information generating circuit 4 as a reception time axis update timing signal e.

The reception time axis information generation circuit 14 determines and outputs the reception time axis information f by resetting at the timing of the reception time axis update timing signal e indicating the end of the frame.

In this way, the frame synchronization code detection timing signal a
is compared with the predicted reception position of this signal, X pips) (X is a positive integer). When received in advance, the detected position error information d output from the frame synchronization code position error detection circuit 12 is , A+l-X, and when the frame synchronization code detection timing signal a is input with a delay of Y bits (Y is a positive integer), the detected position error information @d is the value of A+1+Y. and sends it to the variable delay circuit 13.

The variable delay circuit 13 inputs a timing signal g that precedes A bit from the end of the frame, gives this timing signal g a delay of an amount indicated by the detected position error information d,
The reception time axis information generation circuit 1 uses a signal indicating the end position of the frame corresponding to the positional fluctuation of the frame synchronization code detection timing as the reception time axis update timing signal e.
Send to 4.

The reception time axis information generation circuit 14 is reset at the position indicated by the reception time axis update timing signal e, that is, at the end position of the frame corresponding to the positional fluctuation of the frame synchronization code detection timing, thereby preventing interference with reception data processing. It is possible to determine and output the received time axis information without giving any information.

FIG. 2 is a block diagram illustrating a second embodiment of the present invention. In particular, the means for obtaining the detected position error information d is different from the first embodiment. As shown in FIG. 2, the frame synchronization code detection position error measurement circuit 20 receives a frame synchronization code detection timing signal a and frame synchronization code detection predicted position information A. The frame synchronization code detection position error measuring circuit 20 is composed of a set-reset type flip-flop circuit that inputs the two types of signals and information listed in "-", and a counter that measures the width of the output of this flip-flop circuit. has been done.

Below, this detected position error information id and timing signal g
The variable delay circuit 13 inputs the reception time axis update timing signal e and outputs the reception time axis update timing signal e, and further inputs the reception time axis update timing signal e and outputs the reception time axis information f and the variable delay circuit 1
The configuration and operation of the reception time axis information generating circuit 14 that outputs the timing signal g to the receiver 3 are the same as those described in the first embodiment.

This embodiment is an embodiment in which a time region in which received data is empty exists at the end position of a frame. However, if there is an area where the received data is empty only in the time area other than the end position of the frame, the received data can be processed by generating the timing signal g that is one bit before the empty time position. A circuit that can update and generate received time axis information without causing any disturbance or loss can be easily realized.

〔Effect of the invention〕

The present invention is an apparatus that executes received data processing by detecting a frame synchronization code from received data constituting a frame and determining a received frame time axis using the time indicated by this detection timing. In,
It is possible to generate received frame time axis information corresponding to the reception position of the frame synchronization code.

Therefore, regardless of the insertion position of the frame synchronization code, and even if the code detection position changes, the received data processing will not be affected. That is, it is possible to perform correct received data processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a block diagram showing a second embodiment of the present invention. FIG. 3 is a block diagram illustrating a conventional circuit. 10.20... Frame synchronization code detection position error measurement circuit, 1)... Reception position information temporary storage circuit, ]2...
- Frame synchronization code position error detection circuit, 13... variable delay circuit, 14... reception time axis information generation circuit, a.
... Frame synchronization code detection timing signal, b...
Frame synchronization code insertion position information, C... Frame synchronization code reception position information, d... Detection position error information, e
... Reception time axis update timing signal, f... Reception time axis information, g... Timing signal, h... Frame synchronization code detection predicted position information.

Claims (2)

[Claims] (1) When equipped with a means for extracting a frame synchronization code from a received data string having a frame structure, and a reception time axis information generation circuit that sets a reception frame time axis using the detection timing of this frame synchronization code. In the reception time axis update circuit of the division multiple access device, the relative position error between the detection position of the frame synchronization code inputted from the above extraction means and the predicted detection position of this code set in advance is measured, and the detected position is calculated. The variable delay circuit includes means for outputting error information, and a variable delay circuit that inputs a timing signal and delays the timing signal by an amount specified by the detected position error information output from the output means. The signal output from the variable delay circuit is input to the reception time axis information generation circuit, and this reception time axis information generation circuit is reset to the time indicated by the output signal of the variable delay circuit to designate a new reception frame time axis. A circuit that generates reception time axis information, and a circuit that generates the timing signal at a time that is preceded by the maximum possible bit of the relative position error between the detected position of the frame synchronization code and this detected predicted position. A reception time axis update circuit for a time division multiple access device, comprising: (2) The means for outputting the detected position error information includes a reception position information temporary storage circuit that inputs the frame synchronization code detection timing signal and the frame synchronization code insertion position information and outputs the frame synchronization code reception position information. and a frame synchronization code position error detection circuit that inputs this frame synchronization code reception position information and further inputs a timing signal to determine the amount of variation in the reception position of the frame synchronization code. ) A reception time axis update circuit of the time division multiple access device described in paragraph 1.