JPS5783920A - Logical circuit for trigger control - Google Patents

Logical circuit for trigger control

Info

Publication number
JPS5783920A
JPS5783920A JP55158136A JP15813680A JPS5783920A JP S5783920 A JPS5783920 A JP S5783920A JP 55158136 A JP55158136 A JP 55158136A JP 15813680 A JP15813680 A JP 15813680A JP S5783920 A JPS5783920 A JP S5783920A
Authority
JP
Japan
Prior art keywords
gate
trigger signal
inverting
logical circuit
trigger control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55158136A
Other languages
Japanese (ja)
Inventor
Takafumi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP55158136A priority Critical patent/JPS5783920A/en
Publication of JPS5783920A publication Critical patent/JPS5783920A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Landscapes

  • Logic Circuits (AREA)

Abstract

PURPOSE:To secure inverting operation by applying a trigger signal to a flip- flop through a gate applied with an inverting operation signal for the flip-flop. CONSTITUTION:A trigger signal is generated by a D type FF101, an inverter 102, and an NAND gate 103 and applied to an FF107 composed of NAND gates 105 and 106 through an AND gate 104. An inverting-operating completion information 109b is led out from the output terminal of the NAND gate 106 and applied to the base of a transistor (TR)300 through a level shifting circuit 108. The collector and emitter of the TR300 are connected to the input terminal and output terminal of the AND gate 104, and an L-level trigger signal is held by the AND gate 104 and TR300 until the inverting operation of the FF107 is completed.
JP55158136A 1980-11-12 1980-11-12 Logical circuit for trigger control Pending JPS5783920A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55158136A JPS5783920A (en) 1980-11-12 1980-11-12 Logical circuit for trigger control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55158136A JPS5783920A (en) 1980-11-12 1980-11-12 Logical circuit for trigger control

Publications (1)

Publication Number Publication Date
JPS5783920A true JPS5783920A (en) 1982-05-26

Family

ID=15665053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55158136A Pending JPS5783920A (en) 1980-11-12 1980-11-12 Logical circuit for trigger control

Country Status (1)

Country Link
JP (1) JPS5783920A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0512402U (en) * 1991-07-30 1993-02-19 タキロン株式会社 Garbage collection frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0512402U (en) * 1991-07-30 1993-02-19 タキロン株式会社 Garbage collection frame

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