JPS5335360A - Semiconductor logical circuit - Google Patents

Semiconductor logical circuit

Info

Publication number
JPS5335360A
JPS5335360A JP10954976A JP10954976A JPS5335360A JP S5335360 A JPS5335360 A JP S5335360A JP 10954976 A JP10954976 A JP 10954976A JP 10954976 A JP10954976 A JP 10954976A JP S5335360 A JPS5335360 A JP S5335360A
Authority
JP
Japan
Prior art keywords
logical circuit
signal
semiconductor logical
units
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10954976A
Other languages
Japanese (ja)
Inventor
Takeshi Takeya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10954976A priority Critical patent/JPS5335360A/en
Publication of JPS5335360A publication Critical patent/JPS5335360A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To secure a high-speed operation for a logical circuit in which the inverse output caused by the i-th signal among N-units of logical input signal is controlled by the i-th signal among N-units of control signal corresponding to the logical input signal.
JP10954976A 1976-09-13 1976-09-13 Semiconductor logical circuit Pending JPS5335360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10954976A JPS5335360A (en) 1976-09-13 1976-09-13 Semiconductor logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10954976A JPS5335360A (en) 1976-09-13 1976-09-13 Semiconductor logical circuit

Publications (1)

Publication Number Publication Date
JPS5335360A true JPS5335360A (en) 1978-04-01

Family

ID=14513051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10954976A Pending JPS5335360A (en) 1976-09-13 1976-09-13 Semiconductor logical circuit

Country Status (1)

Country Link
JP (1) JPS5335360A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US678293A (en) * 1900-06-14 1901-07-09 Charles M Barnett Nut-lock.

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US678293A (en) * 1900-06-14 1901-07-09 Charles M Barnett Nut-lock.

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