JPS5778688A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5778688A
JPS5778688A JP15258680A JP15258680A JPS5778688A JP S5778688 A JPS5778688 A JP S5778688A JP 15258680 A JP15258680 A JP 15258680A JP 15258680 A JP15258680 A JP 15258680A JP S5778688 A JPS5778688 A JP S5778688A
Authority
JP
Japan
Prior art keywords
gate
latching circuit
case
written
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15258680A
Other languages
Japanese (ja)
Inventor
Koichi Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15258680A priority Critical patent/JPS5778688A/en
Publication of JPS5778688A publication Critical patent/JPS5778688A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

Landscapes

  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To handle a decoder address latching circuit as an address which is less influenced, in case when an ROM and a PROM are not operated normally, by using said circuit itself as programmable. CONSTITUTION:In case when a data has been written in a floating gate 27, an output signal 24 and an output signal 23 of an inverter are set to a high level and a low level, respectively, and an input signal 18 is always inputted to a latching circuit 29 through a transfer gate 21. On the contrary, in case when no data is written, the output signals 24, 23 are reversed, and the input signal 18 is inputted to the latching circuit 29 through a transfer gate 19. The floating gate 27 becomes a conducting state when a high level is applied to a gate 25, and does not conduct when high voltage is applied to the gate 25 and the drain for a constant time. In this way, the latching circuit 29 is controlled by whether a latch signal is made in-phase or out-of-phase.
JP15258680A 1980-10-30 1980-10-30 Semiconductor device Pending JPS5778688A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15258680A JPS5778688A (en) 1980-10-30 1980-10-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15258680A JPS5778688A (en) 1980-10-30 1980-10-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5778688A true JPS5778688A (en) 1982-05-17

Family

ID=15543694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15258680A Pending JPS5778688A (en) 1980-10-30 1980-10-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5778688A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4803659A (en) * 1987-01-22 1989-02-07 Intel Corporation EPROM latch circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4803659A (en) * 1987-01-22 1989-02-07 Intel Corporation EPROM latch circuit

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