JPS5772340A - Quality evaluating method for single crystal silicon wafer - Google Patents

Quality evaluating method for single crystal silicon wafer

Info

Publication number
JPS5772340A
JPS5772340A JP14869980A JP14869980A JPS5772340A JP S5772340 A JPS5772340 A JP S5772340A JP 14869980 A JP14869980 A JP 14869980A JP 14869980 A JP14869980 A JP 14869980A JP S5772340 A JPS5772340 A JP S5772340A
Authority
JP
Japan
Prior art keywords
single crystal
crystal silicon
silicon wafer
temperature
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14869980A
Other languages
Japanese (ja)
Other versions
JPS6135504B2 (en
Inventor
Hidekatsu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14869980A priority Critical patent/JPS5772340A/en
Publication of JPS5772340A publication Critical patent/JPS5772340A/en
Publication of JPS6135504B2 publication Critical patent/JPS6135504B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Sampling And Sample Adjustment (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To detect easily swirl shaped defects by heating the single crystal silicon wafer in an atmosphere of 1,100-1,200 deg.C for 20-60min and by lowering temperature to less than 700 deg.C with a lowering speed of 0.5-2 deg.C/min. CONSTITUTION:Heat treatment is performed for a single crystal silicon wafer 1 from temperature of 600-700 deg.C, and the temperature is raised to 1,100-1,200 deg.C with a rising speed of 5-10 deg.C/min. Next, impurities of phosphorus are diffused into the wafer 1 using phosphorus oxychloride under temperature of 1,100-1,200 deg.C for 20- 60min, and a diffusion layer is formed on the surface. Further, the ambient temperature of the wafer 1 is reduced to 600-700 deg.C with a speed of 0.5-2 deg.C/min, and the heat treatment is stopped. And, etching is performed to the surface of the wafer 1 in 20-40mu to remove the diffusion layer 2, and thereby the single crystal silicon wafer 3 is obtained.
JP14869980A 1980-10-23 1980-10-23 Quality evaluating method for single crystal silicon wafer Granted JPS5772340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14869980A JPS5772340A (en) 1980-10-23 1980-10-23 Quality evaluating method for single crystal silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14869980A JPS5772340A (en) 1980-10-23 1980-10-23 Quality evaluating method for single crystal silicon wafer

Publications (2)

Publication Number Publication Date
JPS5772340A true JPS5772340A (en) 1982-05-06
JPS6135504B2 JPS6135504B2 (en) 1986-08-13

Family

ID=15458613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14869980A Granted JPS5772340A (en) 1980-10-23 1980-10-23 Quality evaluating method for single crystal silicon wafer

Country Status (1)

Country Link
JP (1) JPS5772340A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0060676A2 (en) * 1981-03-11 1982-09-22 Fujitsu Limited A method for the production of a semiconductor device comprising annealing a silicon wafer
JPS60224239A (en) * 1984-04-20 1985-11-08 Fujitsu Ltd Defect detecting method of thin film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0060676A2 (en) * 1981-03-11 1982-09-22 Fujitsu Limited A method for the production of a semiconductor device comprising annealing a silicon wafer
JPS60224239A (en) * 1984-04-20 1985-11-08 Fujitsu Ltd Defect detecting method of thin film
JPH0342501B2 (en) * 1984-04-20 1991-06-27

Also Published As

Publication number Publication date
JPS6135504B2 (en) 1986-08-13

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