JPS6435911A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6435911A
JPS6435911A JP19002287A JP19002287A JPS6435911A JP S6435911 A JPS6435911 A JP S6435911A JP 19002287 A JP19002287 A JP 19002287A JP 19002287 A JP19002287 A JP 19002287A JP S6435911 A JPS6435911 A JP S6435911A
Authority
JP
Japan
Prior art keywords
layer
diffusion layer
crystal defect
impurity diffusion
circumference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19002287A
Other languages
Japanese (ja)
Inventor
Shizunori Oyu
Masanobu Miyao
Yasuko Takano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19002287A priority Critical patent/JPS6435911A/en
Publication of JPS6435911A publication Critical patent/JPS6435911A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To make it possible to form a groove of excellent controllability and having an impurity introduction layer on which a small area element can be isolated by a method wherein, after an impurity diffusion layer has been formed on the circumferential part of a crystal defect region, a crystal defect diffusion layer only is selectively removed, and then the surface layer of the impurity diffusion layer is removed. CONSTITUTION:After a crystal defect layer 2 has been formed on the desired region of a substrate 1, an impurity introduction layer 3 is formed on the surface of the crystal defect layer 2. Then, an impurity diffusion layer 4 is formed on the substrate 1 located on the circumference of the crystal defect layer 2 by conducting a heat treatment. Then, the crystal defect layer 2 only is selectively removed. Lastly, the surface of the impurity diffusion layer 4 is removed. As the impurity diffusion layer can be formed on the circumference of the processing groove uniformly in an excellent controllable manner, characteristic control can be conducted, and the irregularity in characteristics can also be reduced. Also, the stress of the processing groove can be reduced, and besides, as the impurity diffusion layer in the processing groove and on the circumference can be controlled by ion-implantation and a heat treatment subsequently conducted, the element isolation region can be made smaller in area in the amount of improvement in controllability.
JP19002287A 1987-07-31 1987-07-31 Manufacture of semiconductor device Pending JPS6435911A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19002287A JPS6435911A (en) 1987-07-31 1987-07-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19002287A JPS6435911A (en) 1987-07-31 1987-07-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6435911A true JPS6435911A (en) 1989-02-07

Family

ID=16251068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19002287A Pending JPS6435911A (en) 1987-07-31 1987-07-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6435911A (en)

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