JPS5769931A - Decoder circuit - Google Patents
Decoder circuitInfo
- Publication number
- JPS5769931A JPS5769931A JP14642580A JP14642580A JPS5769931A JP S5769931 A JPS5769931 A JP S5769931A JP 14642580 A JP14642580 A JP 14642580A JP 14642580 A JP14642580 A JP 14642580A JP S5769931 A JPS5769931 A JP S5769931A
- Authority
- JP
- Japan
- Prior art keywords
- decoder
- gate
- activating
- signals
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000872 buffer Substances 0.000 abstract 5
- 230000003213 activating effect Effects 0.000 abstract 3
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14642580A JPS5769931A (en) | 1980-10-20 | 1980-10-20 | Decoder circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14642580A JPS5769931A (en) | 1980-10-20 | 1980-10-20 | Decoder circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5769931A true JPS5769931A (en) | 1982-04-30 |
| JPS632174B2 JPS632174B2 (enExample) | 1988-01-18 |
Family
ID=15407385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14642580A Granted JPS5769931A (en) | 1980-10-20 | 1980-10-20 | Decoder circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5769931A (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03125270U (enExample) * | 1990-03-31 | 1991-12-18 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4971860A (enExample) * | 1972-11-10 | 1974-07-11 | ||
| JPS51147949A (en) * | 1975-06-13 | 1976-12-18 | Fujitsu Ltd | Address inverter circuit |
| JPS533160A (en) * | 1976-06-30 | 1978-01-12 | Oki Electric Ind Co Ltd | Gate circuit |
| JPS5337338A (en) * | 1976-07-02 | 1978-04-06 | Toko Inc | Dynamic decoding circuit |
-
1980
- 1980-10-20 JP JP14642580A patent/JPS5769931A/ja active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4971860A (enExample) * | 1972-11-10 | 1974-07-11 | ||
| JPS51147949A (en) * | 1975-06-13 | 1976-12-18 | Fujitsu Ltd | Address inverter circuit |
| JPS533160A (en) * | 1976-06-30 | 1978-01-12 | Oki Electric Ind Co Ltd | Gate circuit |
| JPS5337338A (en) * | 1976-07-02 | 1978-04-06 | Toko Inc | Dynamic decoding circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS632174B2 (enExample) | 1988-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5634186A (en) | Bipolar memory circuit | |
| JPS5325324A (en) | Address selection system | |
| JPS5783930A (en) | Buffer circuit | |
| JPS5368514A (en) | Driving system for matrix panel | |
| JPS54136239A (en) | Integrated circuit | |
| JPS53149755A (en) | Buffer circuit | |
| JPS5769931A (en) | Decoder circuit | |
| JPS6481082A (en) | Arithmetic circuit | |
| JPS57129536A (en) | Variable logic device | |
| JPS56164631A (en) | Signal line precharging circuit | |
| JPS5376719A (en) | Output buffer circuit with tri-state control | |
| JPS55132130A (en) | Tri-state input circuit | |
| JPS6453396A (en) | Output buffer circuit | |
| JPS52144954A (en) | Inverter circuit | |
| JPS5269520A (en) | Mode switching unit | |
| JPS54116951A (en) | Optical delay circuit | |
| JPS57119523A (en) | Programmable logic array | |
| JPS5567962A (en) | Mode selective switching unit | |
| JPS55122290A (en) | Semiconductor memory device | |
| JPS5520054A (en) | Differential amplifier | |
| JPS56135285A (en) | White level tracking circuit | |
| JPS5329480A (en) | Program controller | |
| JPS54142057A (en) | Logic circuit | |
| JPS53138267A (en) | Output driver circuit | |
| JPS56117308A (en) | Erasing circuit |