JPS5769449A - Digital arithmetic circuit - Google Patents

Digital arithmetic circuit

Info

Publication number
JPS5769449A
JPS5769449A JP55143802A JP14380280A JPS5769449A JP S5769449 A JPS5769449 A JP S5769449A JP 55143802 A JP55143802 A JP 55143802A JP 14380280 A JP14380280 A JP 14380280A JP S5769449 A JPS5769449 A JP S5769449A
Authority
JP
Japan
Prior art keywords
signal
gates
output
gate device
arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55143802A
Other languages
Japanese (ja)
Inventor
Masatoshi Kameyama
Hitoshi Ito
Yoshihiko Sakashita
Osamu Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55143802A priority Critical patent/JPS5769449A/en
Publication of JPS5769449A publication Critical patent/JPS5769449A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To obtain data, obtained by rewriting bits at optional positions of a digital signal in a desired bit pattern, easily at a high speed, by adding a mask register and a gate device to the arithmetic part of a CPU. CONSTITUTION:The parallel output M and output M' of a bit pattern set in a mask register 1 are applied to AND gates 61 and 62 through output data lines 4 and 5 and OR gates 63 and 64 of a gate device 6, and a mask enable signal (m) is applied to the AND gates 61 and 62 through a signal line 7 and the OR gates 63 and 64. When the signal (m) is a ''0'', an A' equal to an AM and a B' equal to a B'M are applied to an arithmetic logical operation circuit 10 through output data lines 2 and 3 respectively to perform the arithmetic of the kind of an indication passed through a control signal line 11, thereby sending an output signal F to an output data line 12. When the signal (m) is a ''1'', on the hand, the gate device 6 only permits input signals A and B to pass through it.
JP55143802A 1980-10-15 1980-10-15 Digital arithmetic circuit Pending JPS5769449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55143802A JPS5769449A (en) 1980-10-15 1980-10-15 Digital arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55143802A JPS5769449A (en) 1980-10-15 1980-10-15 Digital arithmetic circuit

Publications (1)

Publication Number Publication Date
JPS5769449A true JPS5769449A (en) 1982-04-28

Family

ID=15347312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55143802A Pending JPS5769449A (en) 1980-10-15 1980-10-15 Digital arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS5769449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61249136A (en) * 1985-04-27 1986-11-06 Nec Corp Register file integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5350629A (en) * 1976-10-18 1978-05-09 Burroughs Corp High speed shift network

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5350629A (en) * 1976-10-18 1978-05-09 Burroughs Corp High speed shift network

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61249136A (en) * 1985-04-27 1986-11-06 Nec Corp Register file integrated circuit

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