JPS57109046A - Logical processing system - Google Patents

Logical processing system

Info

Publication number
JPS57109046A
JPS57109046A JP18875780A JP18875780A JPS57109046A JP S57109046 A JPS57109046 A JP S57109046A JP 18875780 A JP18875780 A JP 18875780A JP 18875780 A JP18875780 A JP 18875780A JP S57109046 A JPS57109046 A JP S57109046A
Authority
JP
Japan
Prior art keywords
data
length
node
input
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18875780A
Other languages
Japanese (ja)
Inventor
Fumihiro Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18875780A priority Critical patent/JPS57109046A/en
Publication of JPS57109046A publication Critical patent/JPS57109046A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To process special arithmetic at a high speed by comparing each input data mutually with short data length on the basis of a control signal from a data detecting circuit and by outputting output data in accordance with the comparison results. CONSTITUTION:In an input register 1, one input data is set and in an input register 2, the other input data is set. Then, a control part 3 counts and compares the bit length of the node pattern of one data and that of the other data to generate a node-length signal which shows the shorter length. Then, a comparison part 4 compares all shorter node patterns with the high-order l-bit longer node pattern and when the both are coincident, the bit length of the longer data and its node pattern are sent to an output register 5.
JP18875780A 1980-12-26 1980-12-26 Logical processing system Pending JPS57109046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18875780A JPS57109046A (en) 1980-12-26 1980-12-26 Logical processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18875780A JPS57109046A (en) 1980-12-26 1980-12-26 Logical processing system

Publications (1)

Publication Number Publication Date
JPS57109046A true JPS57109046A (en) 1982-07-07

Family

ID=16229231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18875780A Pending JPS57109046A (en) 1980-12-26 1980-12-26 Logical processing system

Country Status (1)

Country Link
JP (1) JPS57109046A (en)

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