JPS5767325A - Analogue-digital converting circuit - Google Patents
Analogue-digital converting circuitInfo
- Publication number
- JPS5767325A JPS5767325A JP14393380A JP14393380A JPS5767325A JP S5767325 A JPS5767325 A JP S5767325A JP 14393380 A JP14393380 A JP 14393380A JP 14393380 A JP14393380 A JP 14393380A JP S5767325 A JPS5767325 A JP S5767325A
- Authority
- JP
- Japan
- Prior art keywords
- output
- analogue
- converter
- logical operation
- operation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To make a high-speed D/A conversion possible, by comparing the ana- logue output of a D/A converter with an analogue signal input and by applying the comparison result to a logical operation circuit group controlled by a shift register and by inputting the output of this circuit group to the D/A converter. CONSTITUTION:Outputs of logical operation circuit groups 41-44 are applied to a D/A converter 9, and an analogue output A0 is compared with an analogue signal input AIN by a comparator 10. The output of the comparator 10 is applied to a D-FF 11 and is delayed by one bit and become digital signal outputs D1-D4 and is applied to logical operation circuit groups 41-44 as output timings of shift registers 21-24. When 5 clock pulses are applied to shift registers 21-24, and A/D conversion is completed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14393380A JPS5767325A (en) | 1980-10-15 | 1980-10-15 | Analogue-digital converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14393380A JPS5767325A (en) | 1980-10-15 | 1980-10-15 | Analogue-digital converting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5767325A true JPS5767325A (en) | 1982-04-23 |
Family
ID=15350445
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14393380A Pending JPS5767325A (en) | 1980-10-15 | 1980-10-15 | Analogue-digital converting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5767325A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6113714A (en) * | 1984-06-19 | 1986-01-22 | バア−−ブラウン コ−ポレ−シヨン | Continuous approximate equation analog-to-digital converter |
JPS6490618A (en) * | 1987-09-28 | 1989-04-07 | Burr Brown Corp | High speed continuous approximation register in analog-to-digital converter |
-
1980
- 1980-10-15 JP JP14393380A patent/JPS5767325A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6113714A (en) * | 1984-06-19 | 1986-01-22 | バア−−ブラウン コ−ポレ−シヨン | Continuous approximate equation analog-to-digital converter |
JPS6490618A (en) * | 1987-09-28 | 1989-04-07 | Burr Brown Corp | High speed continuous approximation register in analog-to-digital converter |
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