JPS5760413A - Monitoring method of programmable logic controller of random acess discrete address diagram system - Google Patents

Monitoring method of programmable logic controller of random acess discrete address diagram system

Info

Publication number
JPS5760413A
JPS5760413A JP55135653A JP13565380A JPS5760413A JP S5760413 A JPS5760413 A JP S5760413A JP 55135653 A JP55135653 A JP 55135653A JP 13565380 A JP13565380 A JP 13565380A JP S5760413 A JPS5760413 A JP S5760413A
Authority
JP
Japan
Prior art keywords
instruction
transfer part
monitor
executed
jump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55135653A
Other languages
Japanese (ja)
Inventor
Yukio Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP55135653A priority Critical patent/JPS5760413A/en
Publication of JPS5760413A publication Critical patent/JPS5760413A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/058—Safety, monitoring
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

PURPOSE:To read a jump processing state from a local display, too, by adding a state of an output updating inhibiting signal by a jump instruction, to input/output states by a logical operation result in case when the instruction is executed, and executing its monitor display. CONSTITUTION:A monitor device 2 inputs a program address range for specifying an instruction group to be monitored by a keyboard 8, and transmits its data to a transfer part 5 of a controller CTL1 from a transfer part 10. The CTL1 receives it, stores a logical operation result in case when the instruction is executed within a program address range designated when the execution is executed, and a monitor data containing an output updating inhibiting signal by a jump instruction, in a buffer memory of the transfer part 5, and transfers the monitor data to the transfer part 10 without discontinuing the operation of a main control part 3. The device 2 decodes the monitor data by a display control part 7, and displays an RADA diagram obtained by adding a processing state of the jump instruction to an object circuit, on a CRT6.
JP55135653A 1980-09-29 1980-09-29 Monitoring method of programmable logic controller of random acess discrete address diagram system Pending JPS5760413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55135653A JPS5760413A (en) 1980-09-29 1980-09-29 Monitoring method of programmable logic controller of random acess discrete address diagram system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55135653A JPS5760413A (en) 1980-09-29 1980-09-29 Monitoring method of programmable logic controller of random acess discrete address diagram system

Publications (1)

Publication Number Publication Date
JPS5760413A true JPS5760413A (en) 1982-04-12

Family

ID=15156810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55135653A Pending JPS5760413A (en) 1980-09-29 1980-09-29 Monitoring method of programmable logic controller of random acess discrete address diagram system

Country Status (1)

Country Link
JP (1) JPS5760413A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979316A (en) * 1982-10-28 1984-05-08 Mitsubishi Electric Corp Sequence control monitoring device
WO1999061986A1 (en) * 1998-05-27 1999-12-02 Mitsubishi Denki Kabushiki Kaisha Peripheral equipment for programmable controller and method for monitoring the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979316A (en) * 1982-10-28 1984-05-08 Mitsubishi Electric Corp Sequence control monitoring device
WO1999061986A1 (en) * 1998-05-27 1999-12-02 Mitsubishi Denki Kabushiki Kaisha Peripheral equipment for programmable controller and method for monitoring the same
US6992644B1 (en) 1998-05-27 2006-01-31 Mitsubishi Denki Kabushiki Kaisha Peripheral device of a programmable controller and monitoring method of the peripheral device

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