JPS5757352A - Multi-stage preceding control system for transfer of data - Google Patents

Multi-stage preceding control system for transfer of data

Info

Publication number
JPS5757352A
JPS5757352A JP13081580A JP13081580A JPS5757352A JP S5757352 A JPS5757352 A JP S5757352A JP 13081580 A JP13081580 A JP 13081580A JP 13081580 A JP13081580 A JP 13081580A JP S5757352 A JPS5757352 A JP S5757352A
Authority
JP
Japan
Prior art keywords
data
memory
access
information
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13081580A
Other languages
Japanese (ja)
Other versions
JPS6034147B2 (en
Inventor
Yasumasa Moriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP13081580A priority Critical patent/JPS6034147B2/en
Publication of JPS5757352A publication Critical patent/JPS5757352A/en
Publication of JPS6034147B2 publication Critical patent/JPS6034147B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To increase the processing speed, by once storing the information or data transferred from a device at the preceding stage into a memory and accessing the next memory prior to the end of the cycle time of the memory to which an access is previously given. CONSTITUTION:First-in/first-out memories (FIFO)6-8 are provided between a central processor of the front stage and a manin storage device 9 of the rear stage that perform the transfer of data. The address information 4a, the writing data information 5a and the reading/writing information 3b' given from the processor 1 are stored in said FIFO memories. In case the next data is already in said FIFO memories, an access request signal 12a is delivered. Thus an access is given to the next memory prior to the end of the cycle time of the memory that received an access previously.
JP13081580A 1980-09-22 1980-09-22 Multi-stage advance control method in data transfer Expired JPS6034147B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13081580A JPS6034147B2 (en) 1980-09-22 1980-09-22 Multi-stage advance control method in data transfer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13081580A JPS6034147B2 (en) 1980-09-22 1980-09-22 Multi-stage advance control method in data transfer

Publications (2)

Publication Number Publication Date
JPS5757352A true JPS5757352A (en) 1982-04-06
JPS6034147B2 JPS6034147B2 (en) 1985-08-07

Family

ID=15043353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13081580A Expired JPS6034147B2 (en) 1980-09-22 1980-09-22 Multi-stage advance control method in data transfer

Country Status (1)

Country Link
JP (1) JPS6034147B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0830502A (en) * 1994-07-20 1996-02-02 Nec Corp Circuit for continuous writing in flash memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0830502A (en) * 1994-07-20 1996-02-02 Nec Corp Circuit for continuous writing in flash memory

Also Published As

Publication number Publication date
JPS6034147B2 (en) 1985-08-07

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