JPS5750400A - Digital data storage processor - Google Patents

Digital data storage processor

Info

Publication number
JPS5750400A
JPS5750400A JP55125720A JP12572080A JPS5750400A JP S5750400 A JPS5750400 A JP S5750400A JP 55125720 A JP55125720 A JP 55125720A JP 12572080 A JP12572080 A JP 12572080A JP S5750400 A JPS5750400 A JP S5750400A
Authority
JP
Japan
Prior art keywords
signal
circuit
selects
selection signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55125720A
Other languages
Japanese (ja)
Inventor
Yoshiki Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55125720A priority Critical patent/JPS5750400A/en
Publication of JPS5750400A publication Critical patent/JPS5750400A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

PURPOSE:To reduce the time required for maintenance and inspection, by providing the test selection signal to ensure the direct storing into an optional storage circuit in the inspection mode. CONSTITUTION:The data of a bus 1 is applied to storage circuits 5-7, and the synchronous signals 2 are counted by a counting circuit 3 to produce a selection signal 4. The signal 4 selects the circuit 5 with the first signal 2 and then the circuit 6 with the next signal 2 respectively, and finally selects the circuit 7. The signal 4 and a test selection signal 11 are switched and selected by a switch 12 to be turned into an effective selection signal 13. The switch 12 selects the signal 4 in the normal mode and the signal 11 in the inspection mode, respectively. Each of the circuits 5-7 fetches and stores the data of the bus 1 only when the signal 13 is applied. Then each of the stored data is supplied to processing circuits 8-10 to receive a prescribed process, respectively.
JP55125720A 1980-09-08 1980-09-08 Digital data storage processor Pending JPS5750400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55125720A JPS5750400A (en) 1980-09-08 1980-09-08 Digital data storage processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55125720A JPS5750400A (en) 1980-09-08 1980-09-08 Digital data storage processor

Publications (1)

Publication Number Publication Date
JPS5750400A true JPS5750400A (en) 1982-03-24

Family

ID=14917084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55125720A Pending JPS5750400A (en) 1980-09-08 1980-09-08 Digital data storage processor

Country Status (1)

Country Link
JP (1) JPS5750400A (en)

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