JPS562027A - Multiple electronic computer unit - Google Patents

Multiple electronic computer unit

Info

Publication number
JPS562027A
JPS562027A JP7647679A JP7647679A JPS562027A JP S562027 A JPS562027 A JP S562027A JP 7647679 A JP7647679 A JP 7647679A JP 7647679 A JP7647679 A JP 7647679A JP S562027 A JPS562027 A JP S562027A
Authority
JP
Japan
Prior art keywords
contacts
output signal
buses
units
cpu2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7647679A
Other languages
Japanese (ja)
Inventor
Kunio Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7647679A priority Critical patent/JPS562027A/en
Publication of JPS562027A publication Critical patent/JPS562027A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain an economical multiple electronic computer unit composed of a small number of elements, by properly changing output signal buses, corresponding to process output units of electronic computers, by an output signal change-over unit equipped with a reverse-current preventing circuit.
CONSTITUTION: Process output signal buses 8 and 9 are provided which correspond to process output units 3 and 5 of CPU2, 4. In change-over unit 6, buses 8 and 9 are provided with contacts 2b and 4b which are open at the time of the fault of CPU2, 4 and contacts 2a and 4a which are closed when the CPUs are in operation, and contacts 2a and 2b, and 4a and 4b are connected to electric power common line 10 in series. Further, buses 8 and 9 are connected to output signal contacts a1Wan and b1Wbn of units 3 and 5 through reverse-current preventing circuit 11 with detour preventive diodes and furthermore connected to process 7 via those contacts. Those contacts are brought under adequate switching control, so that only the output signal of unit 3 or 5 or AND between output signals of units 3 and 5 can be supplied to process 7.
COPYRIGHT: (C)1981,JPO&Japio
JP7647679A 1979-06-18 1979-06-18 Multiple electronic computer unit Pending JPS562027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7647679A JPS562027A (en) 1979-06-18 1979-06-18 Multiple electronic computer unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7647679A JPS562027A (en) 1979-06-18 1979-06-18 Multiple electronic computer unit

Publications (1)

Publication Number Publication Date
JPS562027A true JPS562027A (en) 1981-01-10

Family

ID=13606233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7647679A Pending JPS562027A (en) 1979-06-18 1979-06-18 Multiple electronic computer unit

Country Status (1)

Country Link
JP (1) JPS562027A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116053A (en) * 1983-11-29 1985-06-22 Mitsubishi Electric Corp Process input-output device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116053A (en) * 1983-11-29 1985-06-22 Mitsubishi Electric Corp Process input-output device

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