JPS55118123A - Computer peripheral circuit - Google Patents

Computer peripheral circuit

Info

Publication number
JPS55118123A
JPS55118123A JP2527779A JP2527779A JPS55118123A JP S55118123 A JPS55118123 A JP S55118123A JP 2527779 A JP2527779 A JP 2527779A JP 2527779 A JP2527779 A JP 2527779A JP S55118123 A JPS55118123 A JP S55118123A
Authority
JP
Japan
Prior art keywords
switches
rank
case
highest
peripheral circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2527779A
Other languages
Japanese (ja)
Inventor
Takashi Mizuguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2527779A priority Critical patent/JPS55118123A/en
Publication of JPS55118123A publication Critical patent/JPS55118123A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To avoid the incapability of the system operation by providing the switch to the priority control circuit and then varying temporarily the interruption sequence in case the fault takes place.
CONSTITUTION: Switches 6a and 6b are provided along with their wiring given. Switches 6a and 6b are usually turned toward the side shown by the solid lines. In this case, the sequence of the I/O is set as 3A, 3B...3N. Then the highest-rank I/O 3A becomes faulty, and switches 6a and 6b are turned toward the dotted line side. As a result. I/O 3B is set to the highest rank, and 3A is set to the lowest rank each. Thus I/O 3BW1/O 3N are never affected by the fault of I/O 3A, and accordingly the system can secure the operation by excluding 3A.
COPYRIGHT: (C)1980,JPO&Japio
JP2527779A 1979-03-05 1979-03-05 Computer peripheral circuit Pending JPS55118123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2527779A JPS55118123A (en) 1979-03-05 1979-03-05 Computer peripheral circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2527779A JPS55118123A (en) 1979-03-05 1979-03-05 Computer peripheral circuit

Publications (1)

Publication Number Publication Date
JPS55118123A true JPS55118123A (en) 1980-09-10

Family

ID=12161519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2527779A Pending JPS55118123A (en) 1979-03-05 1979-03-05 Computer peripheral circuit

Country Status (1)

Country Link
JP (1) JPS55118123A (en)

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