JPS5676847A - Microprogram control unit - Google Patents

Microprogram control unit

Info

Publication number
JPS5676847A
JPS5676847A JP15329779A JP15329779A JPS5676847A JP S5676847 A JPS5676847 A JP S5676847A JP 15329779 A JP15329779 A JP 15329779A JP 15329779 A JP15329779 A JP 15329779A JP S5676847 A JPS5676847 A JP S5676847A
Authority
JP
Japan
Prior art keywords
microprogram
delivered
branching
produced
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15329779A
Other languages
Japanese (ja)
Inventor
Yoshiaki Sugiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15329779A priority Critical patent/JPS5676847A/en
Publication of JPS5676847A publication Critical patent/JPS5676847A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To decrease the number of steps of a microprogram and at the same time realize a high-speed branching, by giving a simultaneous test to the branching conditions through the 1-step microprogram and by the signal produced at the arithmetic control line and delivered from the control circuit.
CONSTITUTION: The optional signals produced at the branch signal line 14c1 and delivered from the hardware control circuit 13 are selected in an optional number by the signal produced at the branch selection line 14a1 and delivered from the microprogram control circuit 12. Then a simultaneous test is given to several branching conditions of optional operation types by the signal delivered from the circuit 12 and produced at the arithmetic control line 14bc1. In this case, a simultaneous test is possible for several branching conditions with the 1-step microprogram. Thus the number of steps can be reduced for the microprogram, at the same time realizing a high-speed branching.
COPYRIGHT: (C)1981,JPO&Japio
JP15329779A 1979-11-27 1979-11-27 Microprogram control unit Pending JPS5676847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15329779A JPS5676847A (en) 1979-11-27 1979-11-27 Microprogram control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15329779A JPS5676847A (en) 1979-11-27 1979-11-27 Microprogram control unit

Publications (1)

Publication Number Publication Date
JPS5676847A true JPS5676847A (en) 1981-06-24

Family

ID=15559385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15329779A Pending JPS5676847A (en) 1979-11-27 1979-11-27 Microprogram control unit

Country Status (1)

Country Link
JP (1) JPS5676847A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984549A (en) * 1972-12-20 1974-08-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984549A (en) * 1972-12-20 1974-08-14

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