JPS5750147A - Consecutive data transfer system in character multiplex time division multiplexer - Google Patents
Consecutive data transfer system in character multiplex time division multiplexerInfo
- Publication number
- JPS5750147A JPS5750147A JP55124889A JP12488980A JPS5750147A JP S5750147 A JPS5750147 A JP S5750147A JP 55124889 A JP55124889 A JP 55124889A JP 12488980 A JP12488980 A JP 12488980A JP S5750147 A JPS5750147 A JP S5750147A
- Authority
- JP
- Japan
- Prior art keywords
- consecutive data
- data transfer
- time division
- transfer system
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To transfer consecutive data, by increasing the clock frequency given to a universal asynchronous receiver transmitter (UART). CONSTITUTION:A transmission from a start-stop terminal 4 is received at a period T4 of a UART6, it is superimposed on a high speed line in a period T9 at an MODEM2 and transmitted to a start-stop synchronizing terminal 5 after being the synchronizing time T10 at a UART7. In this case, the condition among the periods, T4>=T9>=T10 are required. Similarly, the similar conditions can be tstablished for the start-stop synchronizing terminals 4 and 5. Generally, the transmitter clock frequency of the UART is 16 times the portrate at terminal, but the required conditions can be satisfied by taking 16 times +alpha for the transmitter clock.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55124889A JPS5750147A (en) | 1980-09-09 | 1980-09-09 | Consecutive data transfer system in character multiplex time division multiplexer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55124889A JPS5750147A (en) | 1980-09-09 | 1980-09-09 | Consecutive data transfer system in character multiplex time division multiplexer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5750147A true JPS5750147A (en) | 1982-03-24 |
Family
ID=14896599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55124889A Pending JPS5750147A (en) | 1980-09-09 | 1980-09-09 | Consecutive data transfer system in character multiplex time division multiplexer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5750147A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS525202A (en) * | 1975-07-02 | 1977-01-14 | Hitachi Ltd | Data transmission |
-
1980
- 1980-09-09 JP JP55124889A patent/JPS5750147A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS525202A (en) * | 1975-07-02 | 1977-01-14 | Hitachi Ltd | Data transmission |
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