JPS5748663A - Average level removing system - Google Patents

Average level removing system

Info

Publication number
JPS5748663A
JPS5748663A JP55123986A JP12398680A JPS5748663A JP S5748663 A JPS5748663 A JP S5748663A JP 55123986 A JP55123986 A JP 55123986A JP 12398680 A JP12398680 A JP 12398680A JP S5748663 A JPS5748663 A JP S5748663A
Authority
JP
Japan
Prior art keywords
signal
converter
analog signal
digital
average
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55123986A
Other languages
Japanese (ja)
Inventor
Shinichi Kitamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55123986A priority Critical patent/JPS5748663A/en
Publication of JPS5748663A publication Critical patent/JPS5748663A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements

Abstract

PURPOSE:To eliminate the need for a costly high speed A/D converter of multibits and lower the cost of production by obtaining the digital value used for calculation of average values by low speed A/D conversion. CONSTITUTION:The output of a low speed A/D converter 61 inputted with an analog signal (a) is inputted to an average level operating circuit 52 consisting of plural registers and adders, and a digital average signal (b') is latched by latch circuits 63, 64. The digital average signal (f') thereof is again converted to an analog signal (f) by a low speed D/A converter 65, and the difference between the analog signal (f) and the analog signal (a) is amplified by a differential amplifier 66. This signal (g) is converted by a high speed A/D converter 67, by which a digital signal (g') for flaw detection is obtained. Thereby, inexpensive circuits are used and the production cost for the device is lowered.
JP55123986A 1980-09-09 1980-09-09 Average level removing system Pending JPS5748663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55123986A JPS5748663A (en) 1980-09-09 1980-09-09 Average level removing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55123986A JPS5748663A (en) 1980-09-09 1980-09-09 Average level removing system

Publications (1)

Publication Number Publication Date
JPS5748663A true JPS5748663A (en) 1982-03-20

Family

ID=14874207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55123986A Pending JPS5748663A (en) 1980-09-09 1980-09-09 Average level removing system

Country Status (1)

Country Link
JP (1) JPS5748663A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02233067A (en) * 1989-03-07 1990-09-14 Sony Corp Television receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02233067A (en) * 1989-03-07 1990-09-14 Sony Corp Television receiver

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