JPS5669924A - Digital processing system - Google Patents

Digital processing system

Info

Publication number
JPS5669924A
JPS5669924A JP14676379A JP14676379A JPS5669924A JP S5669924 A JPS5669924 A JP S5669924A JP 14676379 A JP14676379 A JP 14676379A JP 14676379 A JP14676379 A JP 14676379A JP S5669924 A JPS5669924 A JP S5669924A
Authority
JP
Japan
Prior art keywords
converter
series data
filter
input signal
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14676379A
Other languages
Japanese (ja)
Inventor
Harumitsu Shimizu
Meiki Yahata
Hideo Suzuki
Shunsuke Yoda
Tadamichi Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Toshiba Corp
Nippon Telegraph and Telephone Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Nippon Telegraph and Telephone Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14676379A priority Critical patent/JPS5669924A/en
Publication of JPS5669924A publication Critical patent/JPS5669924A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

PURPOSE:To eliminate a DC offset by convertng an A/D conversion output into series data and by passing it through a low-frequency cutting-off filter. CONSTITUTION:The output voltage of bias circuit 1 is roughly adjusted to the center part of the dynamic range of A/D converter 3 when input signal X(t) is 0V. Input signal X(t) is converted by A/D converter 3 into a digital signal, which is further converted by parallel-series converter 4 into series data. Then, the series data is applied to ditigal low-frequency cutting-off filter 6 to remove its DC offset before it is led to digital arithmetic part 5.
JP14676379A 1979-11-13 1979-11-13 Digital processing system Pending JPS5669924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14676379A JPS5669924A (en) 1979-11-13 1979-11-13 Digital processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14676379A JPS5669924A (en) 1979-11-13 1979-11-13 Digital processing system

Publications (1)

Publication Number Publication Date
JPS5669924A true JPS5669924A (en) 1981-06-11

Family

ID=15415006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14676379A Pending JPS5669924A (en) 1979-11-13 1979-11-13 Digital processing system

Country Status (1)

Country Link
JP (1) JPS5669924A (en)

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