JPS574631A - Demodulating device of digital signal - Google Patents

Demodulating device of digital signal

Info

Publication number
JPS574631A
JPS574631A JP7785780A JP7785780A JPS574631A JP S574631 A JPS574631 A JP S574631A JP 7785780 A JP7785780 A JP 7785780A JP 7785780 A JP7785780 A JP 7785780A JP S574631 A JPS574631 A JP S574631A
Authority
JP
Japan
Prior art keywords
clock
shift
gate
phase
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7785780A
Other languages
Japanese (ja)
Inventor
Ichiro Ogura
Yoshiya Takemura
Chojuro Yamamitsu
Kunihiko Mototani
Akifumi Ide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7785780A priority Critical patent/JPS574631A/en
Publication of JPS574631A publication Critical patent/JPS574631A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To avoid a mistaken correction, by making effective at least either one of the means to detect a shift of phase and the means to correct the shift of phase for a prescribed period. CONSTITUTION:A reproduced signal is supplied from an input terminal 11, and an nF clock [a clock having (n) times as much as the bit frequency of the input data] is produced by a PLL12. Then the reference clock having a frequency equal to the data frequency is produced by a clock generator 14. With this reference clock, the reproduced signal is decoded to the original data through a decoder 13. Furthermore, the information on the shift of phase sent from a detector 15 for shift of clock phase is supplied to the generator 14 via a gate 16. And a control signal is supplied to the gate 16 through an input terminal 17 to open the gate for a certain time to the reproduced data series and to close the gate otherwise.
JP7785780A 1980-06-11 1980-06-11 Demodulating device of digital signal Pending JPS574631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7785780A JPS574631A (en) 1980-06-11 1980-06-11 Demodulating device of digital signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7785780A JPS574631A (en) 1980-06-11 1980-06-11 Demodulating device of digital signal

Publications (1)

Publication Number Publication Date
JPS574631A true JPS574631A (en) 1982-01-11

Family

ID=13645726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7785780A Pending JPS574631A (en) 1980-06-11 1980-06-11 Demodulating device of digital signal

Country Status (1)

Country Link
JP (1) JPS574631A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49107129A (en) * 1973-02-12 1974-10-11

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49107129A (en) * 1973-02-12 1974-10-11

Similar Documents

Publication Publication Date Title
JPS5380105A (en) Digital signal transmission method
JPS57171868A (en) Waveform shaping circuit
DK478488A (en) METHOD AND / OR APPARATUS FOR DEMODULATING A BIPHASE SIGNAL
JPS5753802A (en) Processor of digital signal
JPS5639642A (en) Decoding circuit
JPS56163567A (en) Control circuit for consecutive data block address
ATE40026T1 (en) LOSS CORRECTION CIRCUIT FOR CORRECTING VIDEO SIGNALS DISTURBED BY LOSSES.
JPS57124954A (en) Data playback circuit
JPS5580814A (en) Pcm recorder/reproducer
JPS574631A (en) Demodulating device of digital signal
JPS53136424A (en) Correlative processing system for picture signal
JPS5740788A (en) Recording and reproducing device for smpte code
JPS5584088A (en) Automatic performance device of piano
JPS5673946A (en) Loop constituting system for data transmission system
JPS52131411A (en) Decoding and record control system for picture signal
JPS5584008A (en) Recorder/reproducer of digital signal
JPS5710566A (en) Decoding circuit
JPS552927A (en) Automatic time correction device
JPS56122251A (en) Synchronous control system
JPS57107688A (en) Sampling pulse correcting system
JPS5781752A (en) Demodulating circuit for transmission system of same direction data
JPS54148414A (en) Reproduction system for timing information
JPS5715547A (en) Data receiver
JPS5220507A (en) Tester for automatic train control means
JPS57133783A (en) Slice level setting system