JPS574618A - Flip-flop - Google Patents

Flip-flop

Info

Publication number
JPS574618A
JPS574618A JP7776880A JP7776880A JPS574618A JP S574618 A JPS574618 A JP S574618A JP 7776880 A JP7776880 A JP 7776880A JP 7776880 A JP7776880 A JP 7776880A JP S574618 A JPS574618 A JP S574618A
Authority
JP
Japan
Prior art keywords
input
gate
gates
clock
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7776880A
Other languages
Japanese (ja)
Other versions
JPH0368568B2 (en
Inventor
Rikio Kuribayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7776880A priority Critical patent/JPS574618A/en
Publication of JPS574618A publication Critical patent/JPS574618A/en
Publication of JPH0368568B2 publication Critical patent/JPH0368568B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To facilitate an easy diagnosis for an FF itself and its peipheral logical circuit and at the same time realize a selection for the operations of both an edge trigger type FF and a clock type FF, by adding an OR gate to a gate controlling circuit and turning the input of one side of the OR gate into a mode input. CONSTITUTION:A basic RS-FF10 is formed with two NAND gates 1 and 2 with cross connection given to the input and output. A gate controlling circuit 13 that controls two inputs of the FF10 consists of four NAND gates 3-6 plus OR gates 7 and 8. Thus the clock input CK, data input D and mode input MD are applied to the gates 3 and 4, the gate 6 and the gates 7 and 8, respectively. In case the input D is at O level, the FF10 works as an edge trigger type FF. While the FF has a clock type operation when ''1'' is applied to the input MD.
JP7776880A 1980-06-11 1980-06-11 Flip-flop Granted JPS574618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7776880A JPS574618A (en) 1980-06-11 1980-06-11 Flip-flop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7776880A JPS574618A (en) 1980-06-11 1980-06-11 Flip-flop

Publications (2)

Publication Number Publication Date
JPS574618A true JPS574618A (en) 1982-01-11
JPH0368568B2 JPH0368568B2 (en) 1991-10-29

Family

ID=13643117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7776880A Granted JPS574618A (en) 1980-06-11 1980-06-11 Flip-flop

Country Status (1)

Country Link
JP (1) JPS574618A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI583441B (en) * 2015-07-06 2017-05-21 Nihon Spindle Manufacturing Co Ltd Closed kneading machine

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333566A (en) * 1976-08-09 1978-03-29 Hitachi Ltd Low-power logical circuit
JPS5373952A (en) * 1976-12-14 1978-06-30 Toshiba Corp Flip-flop integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333566A (en) * 1976-08-09 1978-03-29 Hitachi Ltd Low-power logical circuit
JPS5373952A (en) * 1976-12-14 1978-06-30 Toshiba Corp Flip-flop integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI583441B (en) * 2015-07-06 2017-05-21 Nihon Spindle Manufacturing Co Ltd Closed kneading machine

Also Published As

Publication number Publication date
JPH0368568B2 (en) 1991-10-29

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