JPS5741746A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS5741746A
JPS5741746A JP55119590A JP11959080A JPS5741746A JP S5741746 A JPS5741746 A JP S5741746A JP 55119590 A JP55119590 A JP 55119590A JP 11959080 A JP11959080 A JP 11959080A JP S5741746 A JPS5741746 A JP S5741746A
Authority
JP
Japan
Prior art keywords
program
executing
correcting
cpu1
caused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55119590A
Other languages
Japanese (ja)
Inventor
Naoyuki Konishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55119590A priority Critical patent/JPS5741746A/en
Publication of JPS5741746A publication Critical patent/JPS5741746A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To prevent the trouble which is caused by a fault of a memory device, by performing the detecting and correcting arithmetic processes of an error for the program block to be executed next by making use of an idle time of a connection bus that connects a central arithmetic processor and a memory. CONSTITUTION:While a central arithmetic processor (CPU)1 is executing a program, an idle state such as the decoding time of an instruction is caused to a bus line 5. Making use of this idle time, an error detecting and correcting arithmetic process controller 2 reads the next and subsequent program blocks out of a memory device 3 while the CPU1 is executing the first program for instance. The error detecting and correcting arithmetic process is carried out for the read-in program while the CPU1 is executing the first program.
JP55119590A 1980-08-26 1980-08-26 Electronic computer Pending JPS5741746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55119590A JPS5741746A (en) 1980-08-26 1980-08-26 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55119590A JPS5741746A (en) 1980-08-26 1980-08-26 Electronic computer

Publications (1)

Publication Number Publication Date
JPS5741746A true JPS5741746A (en) 1982-03-09

Family

ID=14765133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55119590A Pending JPS5741746A (en) 1980-08-26 1980-08-26 Electronic computer

Country Status (1)

Country Link
JP (1) JPS5741746A (en)

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