JPS5737934A - Binary couter circuit - Google Patents

Binary couter circuit

Info

Publication number
JPS5737934A
JPS5737934A JP11207380A JP11207380A JPS5737934A JP S5737934 A JPS5737934 A JP S5737934A JP 11207380 A JP11207380 A JP 11207380A JP 11207380 A JP11207380 A JP 11207380A JP S5737934 A JPS5737934 A JP S5737934A
Authority
JP
Japan
Prior art keywords
phi
output
signal
input terminal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11207380A
Other languages
Japanese (ja)
Inventor
Kiyoharu Oikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11207380A priority Critical patent/JPS5737934A/en
Publication of JPS5737934A publication Critical patent/JPS5737934A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To reduce the number of elements of a circuit, by connecting a transfer gate TG between a data input terminal and an inverter IV, inputting the input and output terminals of the IV to an FF, and applying a clock signal phi and phi'to the TG and the FF respectively. CONSTITUTION:A TGT is connected between a data input terminal D and an IVI, and the input and output terminals A, B of the IVI are connected to one input of AND gates A1, A2. The output Q' of the FF is fed back to the input terminal D and clock signals phi and phi' are applied to other inputs of the TGT and the gates A1, A2 respectively. When the signal phi is at 1 level, the read-in information Q' is fed back to the input terminal A of the IV. When the signal B at the output terminal B of the IV is at 1, if the phi' is at 1, the Q output of the FF is at 0 and the Q' output is at 1. When the signal phi is at 1, the signal B is inverted to 0, and further, the signal phi' is at 1, the Q output is at 1 and the Q' output is at 0. Thus, the number of the TG, IV can be reduced by one respectively in comparison with conventional methods, allowing high integration of IC and low power consumption.
JP11207380A 1980-08-14 1980-08-14 Binary couter circuit Pending JPS5737934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11207380A JPS5737934A (en) 1980-08-14 1980-08-14 Binary couter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11207380A JPS5737934A (en) 1980-08-14 1980-08-14 Binary couter circuit

Publications (1)

Publication Number Publication Date
JPS5737934A true JPS5737934A (en) 1982-03-02

Family

ID=14577388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11207380A Pending JPS5737934A (en) 1980-08-14 1980-08-14 Binary couter circuit

Country Status (1)

Country Link
JP (1) JPS5737934A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903242A (en) * 1987-05-06 1990-02-20 Nec Corporation Serial access memory circuit with improved serial addressing circuit composed of a shift register
US5008905A (en) * 1988-06-20 1991-04-16 Hughes Aircraft Company Universal shift register employing a matrix of transmission gates

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903242A (en) * 1987-05-06 1990-02-20 Nec Corporation Serial access memory circuit with improved serial addressing circuit composed of a shift register
US5008905A (en) * 1988-06-20 1991-04-16 Hughes Aircraft Company Universal shift register employing a matrix of transmission gates

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