JPS5736354A - Dividing and controlling system for common memory - Google Patents
Dividing and controlling system for common memoryInfo
- Publication number
- JPS5736354A JPS5736354A JP11165680A JP11165680A JPS5736354A JP S5736354 A JPS5736354 A JP S5736354A JP 11165680 A JP11165680 A JP 11165680A JP 11165680 A JP11165680 A JP 11165680A JP S5736354 A JPS5736354 A JP S5736354A
- Authority
- JP
- Japan
- Prior art keywords
- shared memory
- computer
- access
- memory
- dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To prevent wrong access of a shared memory from an abnormal line computer to a normal line computer area and to prevent breakdown of the shared memory by making an arrangement that the memory controlling function can make access to the shared memory or is suppressed in making access, in accordance with processing from each computer. CONSTITUTION:The area of a shared memory 1 corresponding to each computer 15, 16 and 17 constituting a multicomputer system is divided, and stores processing information which is to be stored in each computer 15, 16 and 17. Memory controlling equipments 22, 23 and 24 are connected between each computer 15, 16 and 17 and the shared memory 1, respectively. When constituting control information is changed, the access range to the shared memory 1 is confirmed based on the information and the constituting control information of the other line's computers 15, 16 or 17, and the controlling equipments 22, 23 or 24 are controlled. In this way, wrong access of the shared memory 1 from an abnormal line computer to a normal line computer are prevented and breakdown of the shared memory 1 is prevented.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11165680A JPS5736354A (en) | 1980-08-15 | 1980-08-15 | Dividing and controlling system for common memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11165680A JPS5736354A (en) | 1980-08-15 | 1980-08-15 | Dividing and controlling system for common memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5736354A true JPS5736354A (en) | 1982-02-27 |
Family
ID=14566849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11165680A Pending JPS5736354A (en) | 1980-08-15 | 1980-08-15 | Dividing and controlling system for common memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5736354A (en) |
-
1980
- 1980-08-15 JP JP11165680A patent/JPS5736354A/en active Pending
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